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JFET Operational Amplifier - SiS1057
Wide bandwidth JFET Input Operational Amplifier in bare die form
Rev 1.0
23/06/18
Description
Features:
The SiS1057 JFET input amplifier combines precision
specifications with high speed performance. A slew
rate of 50V/µs with 1.5 µs settling time to 0.01% is
suited for high speed sample + hold circuits and data
converters. Low bias current and offset characteristics
benefit applications requiring greater precision at
speed, such as peak detectors, photodiode amplifiers
and log amplifiers. The device exhibits low voltage
and current noise at either high or low source
impedance . Low drift over temperature delivers
improved stability. This device is characterised over
the full military temperature range.
ƒ Wide gain bandwidth: 20MHz (AV = 5)
ƒ High speed: 50V/µs slew rate, 1.5 µs settling time
ƒ Low noise: 12nv/√Hz (10KHz)
ƒ Low input bias current: 30pA
ƒ Low drift input offset voltage: 1mV, 3µV/°C
ƒ Common-Mode Rejection: 100 dB
ƒ Open-Loop gain: 106 dB
ƒ Differential input voltage range ≤ supply voltage
Ordering Information
The following part suffixes apply:
ƒ No suffix - MIL-STD-883 /2010B Visual Inspection
ƒ H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
ƒ K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
Die Dimensions in µm (mils)
1880 (74)
Supply Formats:
ƒ Default – Die in Waffle Pack (400 per tray capacity)
ƒ Sawn Wafer on Tape – On request
ƒ Unsawn Wafer – On request
ƒ Die Thickness <> 460µm(18 Mils) – On request
ƒ Assembled into Ceramic Package – On request
Mechanical Specification
Die Size
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1880 x 1092
74 x 43
µm
mils
100 x 100
4x4
µm
mils
460 (±20)
18 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
Page 1 of 7
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JFET Operational Amplifier - SiS1057
d
Pad Layout and Functions
Rev 1.0
23/06/18
21
7
34
DIE ID
5
1880µm (74 mils)
Simplified Schematic
6
PAD
FUNCTION
1 BALANCE
2 IN-
3 IN+
4 V-
5 BALANCE
6 OUTPUT
7 V+
CONNECT CHIP BACK TO V-
C
3pF
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JFET Operational Amplifier - SiS1057
Absolute Maximum Ratings1
Rev 1.0
23/06/18
PARAMETER
Supply Voltage
Input Differential Voltage Range
Input Voltage Range2
Output Short Circuit to Ground
Electrostatic Discharge3
Power Dissipation in Still Air
Storage Temperature
Junction Temperature
SYMBOL
VS
VIDR
VI
-
VESD
PD
TSTG
TJ
VALUE
±22
±40
±20
Continuous
±1000
570
-65 to +150
150
UNIT
V
V
V
-
V
mW
°C
°C
1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended
periods, may reduce device reliability.
2. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
3. 100 pF discharged through 1.5-kΩ resistor, Human body model (HBM).
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
DC Supply Voltage
VCC ±15
Operating Temperature
TJ -55
MAX
±20
+125
UNITS
V
°C
DC Electrical Characteristics (-55°C ≤ TJ ≤ +125°C, ±15V ≤ VS ≤ ±20V unless otherwise specified)
PARAMETER
SYMBOL
Input Offset Voltage
Input Offset Voltage
Drift
Change in Drift with
VOS adjust4
Input Offset Current
VIO
ΔVIO /ΔT
ΔTC / VIO
IIO
CONDITIONS
RS = 50Ω,
VCM = 0V
25°C
125°C
RS = 50Ω,
VCM = 0V
VCM = 0V
25°C
125°C
MIN
-
-
-
-
-
-
LIMITS
TYP
1
-
3
0.5
3
-
MAX
2
2.5
5
-
10
10
UNITS
mV
µV/°C
µV/°C
per mV
pA
nA
Input Bias Current5
IIB
VCM = 0V
25°C
125°C
-
-
30
-
50
25
pA
nA
Supply Current
Common Mode Input
Voltage range
ICC
VICR
Vs = ±15V
Vs = ±15V
25°C
-
±11
5
+15.1
-12
6
-
mA
V
4. Temperature Coefficient of the adjusted input offset voltage changes 0.5mV/°C typically for each mV of adjustment from it’s original
unadjusted value. Common-mode rejection and open loop voltage gain are unaffected by offset adjustment.
5. In normal operation junction temperature rises above ambient temperature as a result of internal power dissipation, Pd. TJ = TA + θJA, where
θJA is the thermal resistance from junction to ambient. Use of a heat sink is recommended to minimalize input bias current.
Page 3 of 7
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JFET Operational Amplifier - SiS1057
Rev 1.0
DC
Electrical
Characteristics
(-55°C
TJ
+125°C,
±15V
VS
±20V
unless
otherwise
23/06/18
specified)
PARAMETER
SYMBOL
CONDITIONS
LIMITS
MIN TYP MAX
UNITS
Input Resistance
RIN
TJ = 25°C
- 1012
-
Ω
Large-Signal Open-
Loop Voltage Gain
AVOL
VS = ±15V,
VO = ±10V,
RL ≥ 2KΩ
25°C
125°C
50
50
200
-
-
-
V/mV
Output Voltage Swing
Common-Mode
Rejection Ratio
VO
CMRR
VS = ±15V, RL=10KΩ
VS = ±15V, RL=2KΩ
±12 ±13
±10 ±12
85 100
-
-
-
V
dB
Power Supply
Rejection Ratio
PSSR
85 100
-
dB
AC Electrical Characteristics (TJ = 25°C, VS = ±15V unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
LIMITS
MIN TYP MAX
Slew Rate
SR
AV = 5
40 50
-
Gain Bandwidth
GBW
15 20
-
Settling Time
ts AV = -5, 10V Step 0.01% -
Equivalent Input
Noise Voltage
en
RS = 100Ω
fO = 100Hz
fO = 1KHz
-
-
Equivalent Input
Noise Current
in
RS = 100Ω
fO = 100Hz
fO = 1KHz
-
-
Input Capacitance
CIN
-
1.5
15
12
0.01
0.01
3
-
-
-
-
-
Typical DC Characteristics
UNITS
V/µs
MHz
µS
nV/√Hz
pA/√Hz
pF
FIGURE 1. Input Bias Current
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FIGURE 2. Input Bias Current VCM

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JFET Operational Amplifier - SiS1057
Typical DC Characteristics continued
Rev 1.0
23/06/18
FIGURE 3. Supply Current
FIGURE 4. Voltage Swing
FIGURE 5. Negative Current Limit
FIGURE 6. Positive Current Limit
FIGURE 7. Positive Common-Mode Input Voltage Limit
FIGURE 8. Negative Common-Mode
Input Voltage Limit
Page 5 of 7
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