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ASAHI KASEI
[AK5383]
AK5383
Enhanced Dual Bit ∆Σ 96kHz 24-Bit ADC
GENERAL DESCRIPTION
The AK5383 is a 24bit, 128x oversampling 2ch A/D Converter for professional digital audio systems. The
modulator in the AK5383 uses the new developed Enhanced Dual Bit architecture. This new architecture
achieves the wide dynamic range, while keeping much the same superior distortion characteristics as
conventional Single Bit way. The AK5383 performs 110dB dynamic range, so the device is suitable for
professional studio equipment such as digital mixer, digital VTR etc.
FEATURES
p Enhanced Dual Bit ADC
p Sampling Rate: 1kHz~108kHz
p Full Differential Inputs
p S/(N+D): 103dB
p DR: 110dB
p S/N: 110dB
p High Performance Linear Phase Digital Anti-Alias filter
Passband: 0~21.768kHz(@fs=48kHz)
Ripple: 0.001dB
Stopband: 110dB
p Digital HPF & Offset Calibration for Offset Cancel
p Power Supply: 5V±5%(Analog), 3~5.25V(Digital)
p Power Dissipation: 210mW
p Package: 28pin SOP, VSOP
p AK5393 Pin compatible
SMODE1 SMODE2
12 11
SCLK LRCK FSYNC
14 13
16
VREFL 1
GNDL 2
3
VCOML
4
AINL+
AINL- 5
ZCAL 6
25
AINR+
24
AINR-
26
VCOMR
28
VREFR
GNDR 27
Voltage
Reference
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Voltage
Reference
Serial Output
Interface
15
SDATA
Decimation
Filter
Decimation
Filter
HPF
HPF
19
HPFE
17
MCLK
18 DFS
Controller
Calibration
SRAM
23 22
VA AGND
21
BGND
9 10
CAL RST
78
VD DGND
M0049-E-03
-1-
2000/4

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ASAHI KASEI
n Ordering Guide
AK5383VS
AK5383VF
AKD5383
n Pin Layout
–10 ~ +70°C 28pin SOP
–40 ~ +85°C 28pin VSOP
AK5383 Evaluation Board
[AK5383]
VREFL
GNDL
VCOML
AINL+
AINL-
ZCAL
VD
DGND
CAL
RST
SMODE2
SMODE1
LRCK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top
View
28 VREFR
27 GNDR
26 VCOMR
25 AINR+
24 AINR-
23 VA
22 AGND
21 BGND
20 TEST
19 HPFE
18 DFS
17 MCLK
16 FSYNC
15 SDATA
n Compatibility with AK5393
S/(N+D)
DR, S/N
AK5393
105dB
117dB
AK5383
103dB
110dB
M0049-E-03
-2-
2000/4

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ASAHI KASEI
[AK5383]
No. Pin Name
1 VREFL
2 GNDL
3 VCOML
4 AINL+
5 AINL-
6 ZCAL
7 VD
8 DGND
9 CAL
10 RST
11 SMODE2
12 SMODE1
13 LRCK
PIN/FUNCTION
I/O Function
O Lch Reference Voltage Pin, 3.75V
Normally connected to GNDL with a 10µF electrolytic capacitor and
a 0.1µF ceramic capacitor.
- Lch Reference Ground Pin, 0V
O Lch Common Voltage Pin, 2.75V
I Lch Analog positive input Pin
I Lch Analog negative input Pin
I Zero Calibration Control Pin
This pin controls the calibration reference signal.
"L": VCOML and VCOMR
"H": Analog Input Pins (AINL±, AINR±)
- Digital Power Supply Pin, 3.3V
- Digital Ground Pin, 0V
O Calibration Active Signal Pin
"H" means the offset calibration cycle is in progress. Offset calibration starts
when RST goes "H". CAL goes "L" after 8704 LRCK cycles for DFS="L",
17408 LRCK cycles for DFS ="H".
I Reset Pin
When "L", Digital section is powered-down. Upon returning "H", an
offset calibration cycle is started. An offset calibration cycle should always
be initiated after power-up.
I Serial Interface Mode Select Pin
I MSB first, 2's compliment.
SMODE2 SMODE1
MODE
LRCK
LL
LH
HL
HH
Slave mode : MSB justified
Master mode : Similar to I2S
Slave mode : I2S
Master mode : I2S
: H/L
: H/L
: L/H
: L/H
I/O Left/Right Channel Select Clock Pin
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset
when SMODE1 "H".
M0049-E-03
-3-
2000/4

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ASAHI KASEI
[AK5383]
14 SCLK
15 SDATA
16 FSYNC
17 MCLK
18 DFS
19 HPFE
20 TEST
21 BGND
22 AGND
23 VA
24 AINR-
25 AINR+
26 VCOMR
27 GNDR
28 VREFR
I/O Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
O Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
I/O Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I2S mode, FSYNC is
Don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
I Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
I Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
I High Pass Filter Enable Pin
"L": Disable
"H": Enable
I Test Pin ( pull-down pin)
Should be connected to GND.
- Substrate Ground Pin, 0V
- Analog Ground Pin, 0V
- Analog Supply Pin, 5V
I Rch Analog negative input Pin
I Rch Analog positive input Pin
O Rch Common Voltage Pin, 2.75V
- Rch Reference Ground Pin, 0V
O Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor
Note: All digital inputs should not be left floating.
M0049-E-03
-4-
2000/4

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ASAHI KASEI
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Symbol
min
Power Supplies: Analog
Digital
|BGND-DGND| (Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage
VA
VD
GND
IIN
VINA
-0.3
-0.3
-
-
-0.3
Digital Input Voltage
Ambient Temperature (power applied)
AK5383VS
AK5383VF
Storage Temperature
VIND
Ta
Ta
Tstg
-0.3
-10
-40
-65
Notes: 1. All voltages with respect to ground.
2. AGND, BGND and DGND must be connected to the same analog ground plane.
max
6.0
6.0
0.3
±10
VA+0.3
VD+0.3
70
85
150
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
[AK5383]
Units
V
V
V
mA
V
V
°C
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies: Analog
VA 4.75
(Note 3) Digital
VD 3.0
Notes:1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
5.0
3.3
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
max
5.25
5.25
Units
V
V
M0049-E-03
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2000/4