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a
High End, Multichannel,
32-Bit Floating-Point Audio Processor
SST-Melody®-SHARC®
FEATURES
Super Harvard Architecture Computer (SHARC)
4 Independent Buses for Dual Data, Instruction, and
I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory, Integrated I/O
Peripheral I2S Support for 8 Simultaneous Receive and
Transmit Channels
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
2 External Port, DMA Channels and 8 Serial Port,
DMA Channels
Decodes Industry Standard Formats Using a 32-Bit
Floating Point Implementation for Decoding
Dolby® Digital AC-3, Dolby Digital EX Processing
Dolby Pro Logic®, 96 kHz, Dolby Pro Logic II
Dolby Headphone, Dolby 3/0
DTS® 5.1, DTS-ES®-Discreet 6.1, DTS Matrix and Matrix 3.0,
DTS 96/24®, DTS NEO:6
THX® Ultra, Select, Ultra2, 5.1, 7.1, EX
SRS® Labs Circle Surround IITM, Virtual Loudspeaker
MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode
PCM, PCM 96 kHz
HDCD, MLP*
Delay 7.1, 96 kHz
Bass 7.1, 96 kHz, Bass/Treble 2 Channel
ADI Surround: Club, Music, and Stadium
AAC (LC), AAC (LC) 2 Channel, AAC MP
WaveSurround 5.1 Channel to Headphone, Stereo to
Headphone, Channel to Loudspeaker, Stereo to
Loudspeaker
Downsampling 96 kHz to 48 kHz (2-Channel)
3-Band Equalizer, 2-Channel
Encoders: AC-3 2-Channel Consumer Encoder
Single Chip DSP-Based Implementation of Digital Audio
Algorithms
I2S Compatible Ports
Interface to External SDRAM
Melody and SHARC are registered trademarks of Analog Devices, Inc.
DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater
Systems, Inc.
Dolby and Pro Logic are registered trademarks of Dolby Laboratories
Licensing Corporation.
SRS is a registered trademark and Circle Surround II is a trademark of SRS Labs.
THX is a registered trademark of the THX, Ltd.
*MLP is implemented, not certified.
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
SDRAM
128K ؋ 32,
BOOT ROM
1M ؋ 8
ADC
IRQ
GPIO
SST-Melody-SHARC
SERIAL PORT
DAC
ALGORITHMS
COMMAND
S/PDIF
TRANSMITTER
KERNEL
S/PDIF
RECEIVER
DMA CONNECTION
OR DUAL BUFFER
HOST MICRO
Easy Interfaces to Audio Codecs
96 kHz Processing
Supports Customer Specific Post Processing
Automatic Stream Detection and Code Loading
Easy to Use Software Architecture
Optimized Library of Routines
Host Communication Using 16-Bit Parallel Port or SPI Port
Highly Flexible Serial Ports
SRAM Interface for More Delay
Supports IEC60958 For Bit Streams
8-Channel Output Using TDM Codecs
APPLICATIONS
Home Theater AVR Systems
Automotive Audio Receivers
Video Game Consoles
DVD Players
Cable and Satellite Set-Top Boxes
Multimedia Audio/Video Gateways
GENERAL DESCRIPTION
The SST-Melody-SHARC family of powerful 32-bit Audio Proces-
sors from Analog Devices provides flexible solutions and delivers
a host of features across high end and high fidelity audio systems
to the AV receiver and DVD markets. It includes multichannel
audio decoders, encoders, and post processors for digital
audio designs using DSP chipsets in home theater systems and
automotive audio receivers.
(continued on page 11)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

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SST-Melody-SHARC–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS1
Parameter
VDD
TCASE
VIH
VIL1
VIL2
Test
Conditions
Supply Voltage
Case Operating Temperature
High Level Input Voltage
Low Level Input Voltage2
Low Level Input Voltage3
@ VDD = max
@ VDD = min
@ VDD = min
C Grade
Min Max
3.13 3.60
–40 +100
2.0 VDD + 0.5
–0.5 +0.8
–0.5 +0.7
K Grade
Min Max
Unit
3.13 3.60
0 +85
V
°C
2.0 VDD + 0.5 V
–0.5 +0.8
V
–0.5 +0.7
V
NOTES
1See Environmental Conditions section for information on thermal specifications.
2Applies to input and bidirectional pins: DATA31–0, ADDR23–0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, CS, DMAR1, DMAR2, BR2–1, ID2–0,
RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE.
3Applies to input pin CLKIN.
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
C and K Grades
Min Max
Unit
VOH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZLS
IOZLA
IOZLAR
IOZLC
CIN
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3
Low Level Input Current3
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5
Three-State Leakage Current6
Three-State Leakage Current9
Three-State Leakage Current8
Three-State Leakage Current7
Input Capacitance10, 11
@ VDD = min, IOH = –2.0 mA2
@ VDD = min, IOL = +4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
2.4
V
0.4 V
10 µA
10 µA
150 µA
10 µA
8 µA
150 µA
350 µA
4 mA
1.5 mA
8 pF
NOTES
1Applies to output and bidirectional pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, HBG, REDY, DMAG1, DMAG2, BR2–1, CPA,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0,
PWM_EVENT1, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10.
2See Output Drive Current section for typical drive current capabilities.
3Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID1–0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
4Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI.
5Applies to three-statable pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS,
DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (note that ACK is pulled up internally with 2 kduring reset in a multiprocessor system,
when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
6Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
7Applies to CPA pin.
8Applies to ACK pin when pulled up.
9Applies to ACK pin when keeper latch enabled.
10Guaranteed but not tested.
11Applies to all signal pins.
Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only; functional opera-
tion of the device at these or any other conditions greater than those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
SST-Melody-SHARC
Part Number
ADSST-21065LKS-240
ADSST-21065LCS-240
ADSST-21065LKCA-240
ADSST-21065LKS-264
ADSST-21065LKCA-264
ORDERING GUIDE
Case Temperature
Range
0°C to 85°C
–40°C to +100°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
Instruction
Rate (MHz)
60
60
60
66
66
On-Chip
SRAM (Kbit)
544
544
544
544
544
Operating
Voltage (V)
3.3
3.3
3.3
3.3
3.3
Package
Options
S-208-2
S-208-2
BC-196
S-208-2
BC-196
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
SST-Melody-SHARC features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
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SST-Melody-SHARC
208-LEAD MQFP PIN CONFIGURATIONS
VDD 1
RSF0 2
GND 3
RCLK0 4
DR0A 5
DR0B 6
TFS0 7
TCLK0 8
VDD 9
GND 10
DT0A 11
DT0B 12
RFS1 13
GND 14
RCLK1 15
DR1A 16
DR1B 17
TFS1 18
TCLK1 19
VDD 20
VDD 21
DT1A 22
DT1B 23
PWM EVENT1 24
GND 25
PWM EVENT0 26
BR1 27
BR2 28
VDD 29
CLKIN 30
XTAL 31
VDD 32
GND 33
SDCLK1 34
GND 35
VDD 36
SDCLK0 37
DMAR1 38
DMAR2 39
HBR 40
GND 41
RAS 42
CAS 43
SDWE 44
VDD 45
DQM 46
SDCKE 47
SDA10 48
GND 49
DMAG1 50
DMAG2 51
HBG 52
PIN 1
IDENTIFIER
OO
ADSST-21065L
TOP VIEW
(Not to Scale)
NC = NO CONNECT
–4–
156 VDD
155 GND
154 GND
153 BMS
152 BSEL
151 TCK
150 GND
149 TMS
148 TDI
147 TRST
146 TDO
145 EMU
144 ID0
143 ID1
142 NC
141 VDD
140 VDD
139 GND
138 FLAG4
137 FLAG5
136 FLAG6
135 GND
134 FLAG7
133 DATA31
132 DATA30
131 VDD
130 VDD
129 GND
128 DATA29
127 DATA28
126 DATA27
125 GND
124 VDD
123 DATA26
122 DATA25
121 DATA24
120 VDD
119 GND
118 DATA23
117 DATA22
116 DATA21
115 NC
114 GND
113 DATA20
112 DATA19
111 DATA18
110 VDD
109 DATA17
108 DATA16
107 DATA15
106 GND
105 VDD
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196-BALL CSPBGA PIN CONFIGURATION
SST-Melody-SHARC
14
NC7
13 12 11 10
9
8
7
6
5
4
3
2
NC8 ADDR18 ADDR17 ADDR14 ADDR11 ADDR8 ADDR7 ADDR6 ADDR3 ADDR0 FLAG2 NC2
1
NC1 A
TCK
GND ADDR23 ADDR21 ADDR19 ADDR15 ADDR12 ADDR9 ADDR5 ADDR2 FLAG0 IRQ0
RFS0 DR0A B
TDO
BSEL RESET ADDR22 ADDR20 ADDR16 ADDR13 ADDR10 ADDR4 ADDR1 FLAG3 IRQ2 RCLK0 TCLK0 C
EMU
TRST
TMS
BMS
VDD
VDD
VDD
VDD
VDD FLAG1 IRQ1
DR0B
TFS0 RCLK1 D
FLAG4
ID1
TDI
ID0
VDD
GND
GND
GND
GND
VDD
RFS1 DT0A DT0B TFS1 E
FLAG7 FLAG5 FLAG6 VDD
GND
GND
GND
GND
GND
GND
VDD
DR1A DR1B TCLK1 F
DATA29 DATA30 DATA31 VDD
DATA26 DATA27 DATA28 VDD
DATA23 DATA25 DATA24 VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDD
DT1A
BR2
DT1B
PWM_ G
EVENT1
BR1
PWM_ H
EVENT0
VDD SDCLK1 XTAL CLKIN J
DATA22 DATA20 DATA21 DATA19 VDD
GND
GND
GND
GND
VDD
SDWE
HBR SDCLK0 DMAR1 K
DATA18 DATA17 DATA16 DATA13 DATA8 VDD
VDD
VDD
VDD
VDD DMAG2 SDA10 CAS DMAR2 L
DATA15 DATA14 DATA12 DATA9 DATA5 DATA2 FLAG10 ACK
CPA
RD
CS DMAG1 SDCKE RAS M
NC6 DATA11 DATA10 DATA7 DATA4 DATA1 FLAG11 MS1
GND REDY SBTS BMSTR HBG
DQM N
NC5 DATA6 DATA3 DATA0 FLAG8 FLAG9 MS3
MS2
MS0
SW
WR GND NC4 NC3 P
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