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a
CMOS 66 MHz Monolithic 256؋24
Color Palette RAM-DAC
ADV453
FEATURES
66 MHz Pipelined Operation
Triple 8-Bit D/A Converters
256؋24 Color Palette RAM
3؋24 Overlay Registers
RS-343A/RS-170 Compatible Outputs
؉5 V CMOS Monolithic Construction
40-Pin DIP or Small 44-Pin PLCC Package
Power Dissipation: 1000 mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
40 MHz
GENERAL DESCRIPTION
The ADV453 is a complete analog video output RAM-DAC on
a single monolithic chip. It is specifically designed for high reso-
lution color graphics systems. The part contains a 256 ϫ 24
color lookup table, a 3 ϫ 24 overlay palette as well as triple 8-bit
video D/A converters. The ADV453 is capable of simulta-
neously displaying up to 259 colors, 256 from the lookup table
and three from the overlay registers, out of a total color palette
of 16.8 million addressable colors.
The three overlay registers allow for implementation of overlay-
ing cursors, pull down menus and grids. There is an indepen-
dent, asynchronous MPU bus which allows access to the color
lookup table without affecting the input of video data via the
pixel port. The ADV453 is capable of generating RGB video
output signals which are compatible with RS-343A and RS-170
video standards, without requiring external buffering.
The ADV453 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation. The part is packaged in both a 0.6", 40-pin
DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 66 MHz.
2. Compatible with a wide variety of high resolution color
graphics systems including VGA* and Macintosh II.**
3. Three overlay registers allow for implementation of overlay-
ing cursors, pull down menus and grids.
4. Guaranteed monotonic. Integral and differential nonlineari-
ties guaranteed to be a maximum of ± 1 LSB.
5. Low glitch energy, 50 pV secs.
**VGA is a trademark of International Business Machines Corp.
**Macintosh II is a registered trademark of Apple Computer Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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ADV453–SPECIFICATIONS (VAA = +5 V ؎ 5%, VREF = +1.235 V, RSET = 280 . ISYNC connected to IOG.
All specifications TMIN to TMAX1 unless otherwise noted.)
Parameter
All Versions Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Gray Scale Error
Coding
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
8
±1
±1
± 5%
2
0.8
±1
10
2.4
0.4
20
20
Bits
LSB max
LSB max
Gray Scale max
Binary
V min
V max
µA max
pF typ
V min
V max
µA max
pF typ
Guaranteed Monotonic
VIN = 0.4 V or 2.4 V
ISOURCE = 400 µA
ISINK = 3.2 mA
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on IOR, IOB
Blank Level on IOG
Sync Level on IOG
LSB Size
DAC to DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
POWER SUPPLY
Supply Voltage, VAA
Supply Current, IAA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Clock and Data Feedthrough2, 3
Glitch Impulse2, 3
DAC-to-DAC Crosstalk
15
22
17.69
20.40
16.74
18.50
0.95
1.90
0
50
6.29
8.96
0
50
69.1
5
–1
+1.4
10
30
1.14/1.26
–5
4.75/5.25
275
250
0.5
1375
1250
–30
50
–23
mA min
mA max
mA min
mA max
mA min
mA max
mA min
mA max
µA min
µA max
mA min
mA max
µA min
µA max
µA typ
% max
V min
V max
ktyp
pF typ
V min/V max
mA typ
V min/V max
mA max
mA max
%/% max
mW max
mW max
dB typ
pV secs typ
dB typ
Typically 19.05 mA
Typically 17.62 mA
Typically 1.44 mA
Typically 5 µA
Typically 7.62 mA
Typically 5 µA
Typically 2%
IOUT = 0 mA
Typically 220 mA, 66 MHz Parts
Typically 190 mA, 40 MHz Parts
Typically 0.12%/%, f = 1 kHz, COMP = 0.1 µF
Typically 1000 mW, 66 MHz Parts
Typically 900 mW, 40 MHz Parts
NOTES
1Temperature range (TMIN to TMAX); 0°C to +70°C.
2TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load 10 pF, 37.5 . D0–D7 output load 50 pF. See timing notes in Figure 2.
3Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 k resistor to
ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, –3 dB test bandwidth = 2 ϫ clock rate.
Specifications subject to change without notice.
–2– REV. B

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ADV453
TIMING CHARACTERISTICS1
(VAA = +5 V ؎ 5%, VREF = +1.235
All specifications TMIN to TMAX2.)
V,
RSET
=
280
.
ISYNC
connected
to
IOG.
Parameter
66 MHz Version
40 MHz Version
Units
Conditions/Comments
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t173
tPD
tSK
66
35
35
25
10
100
15
50
35
0
5
2
15
5
5
20
30
3
25
2ϫt12
1
2
40
35
35
25
10
100
15
50
35
0
7
3
25
7
7
20
30
3
25
2ϫt12
1
2
MHz max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns typ
ns typ
ns max
ns typ
ns max
Clock Rate
CS, C0, C1 Setup Time
CS, C0, C1 Hold Time
RD, WR High Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
WR Low Time
Write Data Setup Time
Write Data Hold Time
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Settling Time
Pipeline Delay
Analog Output Skew
NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load 10 pF, 37.5 . D0–D7 output load 50 pF. See timing notes in Figure 2.
2Temperature Range (TMIN to TMAX); 0°C to +70°C.
3Settling time does not include clock and data feedthrough. For this test, the digital inputs have a 1 k resistor to ground and are driven by 74HC logic.
Specifications subject to change without notice.
Figure 1. MPU Read/Write Timing
REV. B
Figure 2. Video Input/Output Timing
–3–

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ADV453
ABSOLUTE MAXIMUM RATINGS1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220°C
IOR, IOB, IOG to GND2 . . . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
ORDERING GUIDE
Model
Temperature
Range
Speed
ADV453KN66
ADV453KN40
ADV453KP66
ADV453KP40
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
66 MHz
40 MHz
66 MHz
40 MHz
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
Package
Option*
N-40A
N-40A
P-44A
P-44A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol Min Typ Max
Power Supply
Ambient Operating Temperature
Output Load
Reference Voltage
VAA
TA
RL
VREF
4.75 5.00 5.25
0 +70
37.5
1.14 1.235 1.26
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV453 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Units
Volts
°C
Volts
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
DIP PLCC
–4– REV. B

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ADV453
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
SYNC
CLOCK
P0–P7
OL0–OL1
IOR, IOG, IOB
ISYNC
FS ADJUST
COMP
VREF
VAA
GND
CS
WR
RD
C0, C1
D0–D7
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs to
the blanking level, as shown in Table V. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is at logical zero, the pixel inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE cur-
rent source on the ISYNC output (see Figure 5). SYNC does not override any other control or data input, as
shown in Table V; therefore, it should only be asserted during the blanking interval. SYNC is latched on the ris-
ing edge of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the P0–P7 and OL0–OL1 data inputs as well
as the SYNC and BLANK control inputs. It is typically the pixel clock rate of the video system. CLOCK should
be driven by a dedicated TTL buffer.
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. P0–P7 pixel select inputs are latched on the rising
edge of CLOCK. P0 is the LSB. Unused pixel select inputs should be connected to GND.
Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color infor-
mation (see Table IV), i.e., the 256ϫ24 color palette or the 3ϫ24 overlay palette. When accessing the overlay
palette, the P0–P7 inputs are ignored. OL0–OL1 are latched on the rising edge of CLOCK. OL0 is the LSB. Un-
used inputs should be connected to GND.
Red, green and blue current outputs. These high impedance current sources are capable of directly driving a dou-
bly terminated 75 coaxial cable, as shown in Figure 4a. All three current outputs should have similar output
loads whether or not they are all being used.
Sync current output. This high impedance current source can be directly connected to the IOG output (see Fig-
ure 3). This allows sync information to be encoded onto the green channel. ISYNC does not output any current
while SYNC is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by:
ISYNC (mA) = 1,728* VREF(V)/RSET().
If sync information is not required on the green channel, ISYNC should be connected to GND.
Full scale adjust control. A resistor (RSET) connected between this pin and GND (see Figure 6) controls the mag-
nitude of the full scale video signal. Note that the IRE relationships in Figure 5 are maintained, regardless of the
full scale output current.
The relationship between RSET and the full scale output current on IOG (assuming ISYNC is connected to IOG) is
given by:
IOG (mA) = (K + 326 + 1,728)* VREF(V)/RSET()
The relationship between RSET and the full scale output current on IOR and IOB is given by:
IOR, IOB (mA) = (K + 326)* VREF(V)/RSET()
where K = 3,993
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor
must be connected between COMP and VAA (Figure 6).
Voltage reference input. An external 1.235 V voltage reference must be connected to this pin. The use of an ex-
ternal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected
between VREF and VAA (Figure 6.)
Analog power supply (5 V ± 5%). All VAA pins on the ADV453 must be connected.
Analog ground. All GND pins must be connected.
Chip select control input (TTL compatible). CS must be at logical zero to enable the reading and writing of data
to and from the device. The IOR, IOG and IOB outputs are forced to the black level while CS is at logical zero.
Note that the ADV453 will not operate properly if CS, RD and WR are simultaneously at logical zero.
Write control input (TTL compatible). CS and WR must both be at logical zero when writing data to the device.
D0–D7 data is latched on the rising edge of WR or CS. See Figure 1.
Read control input (TTL compatible). CS and RD must both be at logical zero when reading data from the de-
vice. See Figure 1.
Command control inputs (TTL compatible). C0 and C1 specify the type of read or write operation being carried
out, i.e., address register, color palette RAM or overlay registers read or write operations. See Tables I, II, III.
Data bus (TTL compatible). Data is transferred to and from the address register, the color palette RAM and the
overlay registers over this 8-bit bidirectional data bus. D0 is the least significant bit.
REV. B
–5–