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inter
Introduction to
the 80386
~ncluding
the 80386
Data Sheet
April 1986

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Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which
may appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, GENIUS, i,~,
ICE, iCEL, iCS, iDBp, iDIS, 12 1CE, iLBX, im, iMDDX, iMMX, Insite, Intel, intel,
intelBOS, Intelevision, inteligent Identifier, inteligent Programming, Intellec,
Intellink, iOSP, iPDS, iPSC, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library
Manager, MAP-NET, MeS, Megachassis, MICROMAINFRAME, MULTIBUS,
MULTICHANNEL, MULTI MODULE, ONCE, OpenNET, OTp, PC-BUBBLE,
Plug-A-Bubble, PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming,
Ripplemode, RMX/80, RUPI, Seamless, SLD, UPI, and VLSiCEL, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or UPI and a numerical suffix,
4-SITE.
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Mohawk Data Sciences Corporation.
'MULTI BUS is a patented Intel bus.
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©INTEL CORPORATION 1986
3/86

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TABLE OF CONTENTS
BOOK I
CHAPTER 1
HIGHLIGHTS
1.1 32-bit Architectu re .............................................................. 1-1
1.2 High-performance Implementation ............................................... 1-1
1.3 Virtual Memory Support ........................................................ 1~3
1.4 Configurable Protection ........................................................ 1-3
1.5 Extended Debugging Support ................................................... 1-3
1.6 Object Code Compatibility ...................................................... 1-4
1.7 Summary ..................................................................... 1-4
CHAPTER 2
APPLICATION ARCHITECTURIE
2.1 Registers ...................................................................... 2-1
2.1.1 General Registers ........................................................... 2-1
2.1.2 Flags and Instruction Pointer ................................................. 2-1
2.1.3 Numeric Coprocessor Registers .............................................. 2-2
2.2 Memory and Logical Addressing ................................................. 2-3
2.2.1 Segments .................................................................. 2-3
2.2.2 Logical Addresses .......................................................... 2-3
2.2.3 Segment and Descriptor Registers ............................................ 2-4
2.2.4 Addressing Modes .......................................................... 2-5
2.3 Data Types and Instructions ..................................................... 2-6
2.3.1 Principal Data Types ........................................................ 2-6
2.3.2 Numeric Coprocessor Data Types ............................................ 2-7
2.3.3 Other Instructions .......................................................... 2-7
2.3.3.1 Stack Instructions ....................................................... 2-7
2.3.3.2 Control Transfer Instructions ............................................. 2-8
2.3.3.3 Miscellaneous Instructions ............................................... 2-10
CHAPTER 3
SYSTEM ARCHITECTURE
3.1 System Registers ............................................................... 3-1
3.2 Multitasking ................................................................... 3-1
3.2.1 Task State Segment ......................................................... 3-2
3.2.2 Task Switching ............................................................. 3-2
3.3 Addressing .................................................................... 3-3
3.3.1 Address Translation Overview ................................................ 3-3
3.3.2 Segments ................................................................. 3-4
3.3.3 Pages ..................................................................... 3-7
3.3.4 Virtual Memory ............................................................. 3-8
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3.4 Protection ................................................................. 3-10
3.4.1 Privilege ................................................................ 3-10
3.4.2 Privileged Instructions .................................................... 3-12
3.4.3 Segment Protection ...................................................... 3-12
3.4.4 Page Protection ......................................................... 3-13
3.5 System Calls ............................................................... 3-13
3.6 Interrupts and Exceptions .................................................... 3-14
3.6.1 Interrupt Descriptor Table ................................................. 3-15
3.6.2 Debug Exceptions and Registers ........................................... 3-16
3.7 Input/Output ............................................................... 3-17
CHAPTER 4
ARCHITECTURAL COMPATIBILITY
4.1 80286 Compatibility ......................................................... 4-1
4.2 Real and Virtual 86 Modes .................................................... 4-1
CHAPTER 5
HARDWARE IMPLEMENTATION
5.1 Internal Design ............................................................. 5-1
5.2 External Interface ........................................................... 5-3
5.2.1 Clock .................................................................. 5-3
5.2.2 Data and Address Buses .................................................. 5-3
5.2.3 Bus Cycle Definition ..................................................... 5-4
5.2.4 Bus Cycle Control ....................................................... 5-4
5.2.5 Dynamic Bus Sizing ...................................................... 5-7
5.2.6 Processor Status and Control .............................................. 5-7
5.2.7 Coprocessor Control ..................................................... 5-7
BOOK II
80386 High Performance Microprocessor with Integrated Memory Management .............. 1
iv