80386DX.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 80386DX 데이타시트 다운로드

No Preview Available !

Intel386TM DX MICROPROCESSOR
32-BIT CHMOS MICROPROCESSOR
WITH INTEGRATED MEMORY MANAGEMENT
Y Flexible 32-Bit Microprocessor
8 16 32-Bit Data Types
8 General Purpose 32-Bit Registers
Y Very Large Address Space
4 Gigabyte Physical
64 Terabyte Virtual
4 Gigabyte Maximum Segment Size
Y Integrated Memory Management Unit
Virtual Memory Support
Optional On-Chip Paging
4 Levels of Protection
Fully Compatible with 80286
Y Object Code Compatible with All 8086
Family Microprocessors
Y Virtual 8086 Mode Allows Running of
8086 Software in a Protected and
Paged System
Y Hardware Debugging Support
Y Optimized for System Performance
Pipelined Instruction Execution
On-Chip Address Translation Caches
20 25 and 33 MHz Clock
40 50 and 66 Megabytes Sec Bus
Bandwidth
Y Numerics Support via Intel387TM DX
Math Coprocessor
Y Complete System Development
Support
Software C PL M Assembler
System Generation Tools
Debuggers PSCOPE ICETM-386
Y High Speed CHMOS IV Technology
Y 132 Pin Grid Array Package
Y 132 Pin Plastic Quad Flat Package
(See Packaging Specification Order 231369)
The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications
and operating systems such as MS-DOS and Windows The 32-bit registers and data paths support 32-bit
addresses and data types The processor addresses up to four gigabytes of physical memory and 64 terabytes
(2 46) of virtual memory The integrated memory management and protection architecture includes address
translation registers multitasking hardware and a protection mechanism to support operating systems Instruc-
tion pipelining on-chip address translation ensure short average instruction execution times and maximum
system throughput
The Intel386 DX CPU offers new testability and debugging features Testability features include a self-test and
direct access to the page translation cache Four new breakpoint registers provide breakpoint traps on code
execution or data accesses for powerful debugging of even ROM-based systems
Object-code compatibility with all 8086 family members (8086 8088 80186 80188 80286) means the
Intel386 DX offers immediate access to the world’s largest microprocessor software base
Intel386TM DX Pipelined 32-Bit Microarchitecture
Intel386TM DX and Intel387TM DX are Trademarks of Intel Corporation
MS-DOS and Windows are Trademarks of MICROSOFT Corporation
231630 – 49
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
December 1995
Order Number 231630-011

No Preview Available !

No Preview Available !

Intel386TM DX MICROPROCESSOR
32-BIT CHMOS MICROPROCESSOR
WITH INTEGRATED MEMORY MANAGEMENT
CONTENTS
1 PIN ASSIGNMENT
1 1 Pin Description Table
2 BASE ARCHITECTURE
2 1 Introduction
2 2 Register Overview
2 3 Register Descriptions
2 4 Instruction Set
2 5 Addressing Modes
2 6 Data Types
2 7 Memory Organization
2 8 I O Space
2 9 Interrupts
2 10 Reset and Initialization
2 11 Testability
2 12 Debugging Support
3 REAL MODE ARCHITECTURE
3 1 Real Mode Introduction
3 2 Memory Addressing
3 3 Reserved Locations
3 4 Interrupts
3 5 Shutdown and Halt
4 PROTECTED MODE ARCHITECTURE
4 1 Introduction
4 2 Addressing Mechanism
4 3 Segmentation
4 4 Protection
4 5 Paging
4 6 Virtual 8086 Environment
5 FUNCTIONAL DATA
5 1 Introduction
5 2 Signal Description
5 2 1 Introduction
5 2 2 Clock (CLK2)
5 2 3 Data Bus (D0 through D31)
5 2 4 Address Bus (BEO through BE3 A2 through A31)
5 2 5 Bus Cycle Definition Signals (W R D C M IO LOCK )
5 2 6 Bus Control Signals (ADS READY NA BS16 )
5 2 7 Bus Arbitration Signals (HOLD HLDA)
5 2 8 Coprocessor Interface Signals (PEREQ BUSY ERROR )
5 2 9 Interrupt Signals (INTR NMI RESET)
5 2 10 Signal Summary
PAGE
5
6
8
8
8
9
15
18
20
22
23
24
27
28
28
32
32
33
34
34
34
34
34
35
36
46
52
56
61
61
61
61
62
62
62
63
64
65
65
66
67
3

No Preview Available !

CONTENTS
5 FUNCTIONAL DATA (Continued)
5 3 Bus Transfer Mechanism
5 3 1 Introduction
5 3 2 Memory and I O Spaces
5 3 3 Memory and I O Organization
5 3 4 Dynamic Data Bus Sizing
5 3 5 Interfacing with 32- and 16-bit Memories
5 3 6 Operand Alignment
5 4 Bus Functional Description
5 4 1 Introduction
5 4 2 Address Pipelining
5 4 3 Read and Write Cycles
5 4 4 Interrupt Acknowledge (INTA) Cycles
5 4 5 Halt Indication Cycle
5 4 6 Shutdown Indication Cycle
5 5 Other Functional Descriptions
5 5 1 Entering and Exiting Hold Acknowledge
5 5 2 Reset during Hold Acknowledge
5 5 3 Bus Activity During and Following Reset
5 6 Self-test Signature
5 7 Component and Revision Identifiers
5 8 Coprocessor Interface
5 8 1 Software Testing for Coprocessor Presence
6 INSTRUCTION SET
6 1 Instruction Encoding and Clock Count Summary
6 2 Instruction Encoding Details
7 DESIGNING FOR ICETM-386 DX EMULATOR USE
8 MECHANICAL DATA
8 1 Introduction
8 2 Package Dimensions and Mounting
8 3 Package Thermal Specification
9 ELECTRICAL DATA
9 1 Introduction
9 2 Power and Grounding
9 3 Maximum Ratings
9 4 D C Specifications
9 5 A C Specifications
10 REVISION HISTORY
NOTE
This is revision 011 This supercedes all previous revisions
4
PAGE
67
67
68
69
69
70
71
71
71
74
76
87
88
89
90
90
90
90
92
92
94
94
95
95
110
117
119
119
119
122
123
123
123
124
124
125
137

No Preview Available !

Intel386TM DX MICROPROCESSOR
1 PIN ASSIGNMENT
The Intel386 DX pinout as viewed from the top side
of the component is shown by Figure 1-1 Its pinout
as viewed from the Pin side of the component is
Figure 1-2
VCC and GND connections must be made to multi-
ple VCC and VSS (GND) pins Each VCC and VSS
must be connected to the appropriate voltage level
The circuit board should include VCC and GND
planes for power distribution and all VCC and VSS
pins must be connected to the appropriate plane
NOTE
Pins identified as ‘‘N C ’’ should remain completely
unconnected
231630 – 33
231630 – 34
Figure 1-1 Intel386TM DX PGA
Pinout View from Top Side
Figure 1-2 Intel386TM DX PGA
Pinout View from Pin Side
Table 1-1 Intel386TM DX PGA Pinout Functional Grouping
Signal Pin
A2 C4
A3 A3
A4 B3
A5 B2
A6 C3
A7 C2
A8 C1
A9 D3
A10 D2
A11 D1
A12 E3
A13 E2
A14 E1
A15 F1
A16 G1
A17 H1
A18 H2
A19 H3
A20 J1
A21 K1
A22 K2
A23 L1
Signal Pin
A24
A25
A26
A27
A28
A29
A30
A31
ADS
BE0
BE1
BE2
BE3
BS16
BUSY
CLK2
D0
D1
D2
D3
D4
D5
L2
K3
M1
N1
L3
M2
P1
N2
E14
E12
C13
B13
A13
C14
B9
F12
H12
H13
H14
J14
K14
K13
Signal Pin
D6 L14
D7 K12
D8 L13
D9 N14
D10 M12
D11 N13
D12 N12
D13 P13
D14 P12
D15 M11
D16 N11
D17 N10
D18 P11
D19 P10
D20 M9
D21 N9
D22 P9
D23 N8
D24 P7
D25 N6
D26 P5
D27 N5
Signal Pin
D28
D29
D30
D31
DC
ERROR
HLDA
HOLD
INTR
LOCK
M IO
NA
NMI
PEREQ
READY
RESET
VCC
M6
P4
P3
M5
A11
A8
M14
D14
B7
C10
A12
D13
B8
C8
G13
C9
A1
A5
A7
A10
A14
C5
Signal Pin
VCC C12
D12
G2
G3
G12
G14
L12
M3
M7
M13
N4
N7
P2
P8
VSS A2
A6
A9
B1
B5
B11
B14
C11
Signal Pin
VSS
WR
NC
F2
F3
F14
J2
J3
J12
J13
M4
M8
M10
N3
P6
P14
B10
A4
B4
B6
B12
C6
C7
E13
F13
5