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State-of-the-Art EPIC-ΙΙBBiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (− 32-mA IOH,
64-mA IOL )
Package Options Include Plastic
Small-Outline ((DW)) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS070D − JULY 1991 − REVISED JULY 1994
SN54ABT652 . . . JT PACKAGE
SN74ABT652 . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 CLKBA
22 SBA
21 OEBA
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
SN54ABT652 . . . FK PACKAGE
(TOP VIEW)
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the ABT652.
4 3 2 1 28 27 26
A1 5
25 OEBA
A2 6
24 B1
A3 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 11
19 B5
12 13 14 15 16 17 18
NC − No internal connection
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The SN74ABT652 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
Copyright 1994, Texas Instruments Incorporated
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SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS070D − JULY 1991 − REVISED JULY 1994
description (continued)
The SN54ABT652 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ABT652 is characterized for operation from − 40°C to 85°C.
OEAB
OEBA
INPUTS
CLKAB CLKBA
SAB
FUNCTION TABLE
DATA I/O†
SBA A1 THRU A8
B1 THRU B8
OPERATION OR FUNCTION
L
H
H or L
H or L
X
X
Input
Input
Isolation
LH
XX
Input
Input
XH
H or L X X
Input
Unspecified‡
HH
X‡ X
Input
Output
L
X H or L
X X Unspecified‡
Input
LL
X X‡
Output
Input
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
LL
X
X XL
Output
Input
Real-time B data to A bus
LL
X H or L X H
Output
Input
Stored B data to A bus
HH
X
X LX
Input
Output
Real-time A data to B bus
H H H or L X H X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

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SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS070D − JULY 1991 − REVISED JULY 1994
3 21
1 23 2
OEAB OEBA CLKAB CLKBA SAB
LL
XXX
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
3 21 1 23 2
OEAB OEBA CLKAB CLKBA SAB
HH X X L
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
3
OEAB
X
L
L
21 1 23 2
OEBA CLKAB CLKBA SAB
H XX
X XX
H ↑↑X
STORAGE FROM
A, B, OR A AND B
22
SBA
X
X
X
3 21
OEAB OEBA
HL
1
CLKAB
L
23 2
CLKBA SAB
LH
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
Pin numbers shown are for the DB, DW, JT, and NT packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
2−3

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SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS070D − JULY 1991 − REVISED JULY 1994
logic symbol
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
4
A1
5
A2
6
A3
7
A4
8
A5
9
A6
10
A7
11
A8
EN1 [BA]
EN2 [AB]
C4
G5
C6
G7
1 5 4D
1 51
6D 7 1
2
17
20
B1
19
B2
18
B3
17
B4
16
B5
15
B6
14
B7
13
B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, and NT packages.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

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logic diagram (positive logic)
OEBA 21
3
OEAB
23
CLKBA
SBA 22
1
CLKAB
2
SAB
One of Eight
Channels
4
A1
1D
C1
SN54ABT652, SN74ABT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS070D − JULY 1991 − REVISED JULY 1994
1D
C1
20
B1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, and NT packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
2−5