• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
• Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
• High-Drive Outputs (− 32-mA IOH,
64-mA IOL )
• Package Options Include Plastic
Small-Outline ((DW)) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3ĆSTATE OUTPUTS
SCBS070D − JULY 1991 − REVISED JULY 1994
SN54ABT652 . . . JT PACKAGE
SN74ABT652 . . . DB, DW, OR NT PACKAGE
SN54ABT652 . . . FK PACKAGE
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the ′ABT652.
4 3 2 1 28 27 26
12 13 14 15 16 17 18
NC − No internal connection
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The SN74ABT652 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
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Copyright 1994, Texas Instruments Incorporated