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SN74ABT3612
64 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
D Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D Two Independent 64 × 36 Clocked FIFOs
Buffering Data in Opposite Directions
D Mailbox-Bypass Register for Each FIFO
D Programmable Almost-Full and
Almost-Empty Flags
D Microprocessor Interface Control Logic
D EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
D EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
D Passive Parity Checking on Each Port
D Parity Generation Can Be Selected for Each
Port
D Low-Power Advanced BiCMOS Technology
D Supports Clock Frequencies up to 67 MHz
D Fast Access Times of 10 ns
D Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is
stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each
port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or
more devices can be used in parallel to create wider datapaths.
The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock
that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are
two-stage synchronized to the port clock that reads data from its array.
The SN74ABT3612 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
D FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number
SCAA007)
D Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
D Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1998, Texas Instruments Incorporated
1

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SN74ABT3612
64 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
PCB PACKAGE
(TOP VIEW)
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC – No internal connection
90 B22
89 B21
88 GND
87 B20
86 B19
85 B18
84 B17
83 B16
82 B15
81 B14
80 B13
79 B12
78 B11
77 B10
76 GND
75 B9
74 B8
73 B7
72 VCC
71 B6
70 B5
69 B4
68 B3
67 GND
66 B2
65 B1
64 B0
63 EFB
62 AEB
61 AFB
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SN74ABT3612
64 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
PQ PACKAGE†
(TOP VIEW)
GND
AEA
EFA
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118
131 129 127 125 123 121 119 117
18 116
19 115
20 114
21 113
22 112
23 111
24 110
25 109
26 108
27 107
28 106
29 105
30 104
31 103
32 102
33 101
34 100
35 99
36 98
37 97
38 96
39 95
40 94
41 93
42 92
43 91
44 90
45 89
46 88
47 87
48 86
49 85
50 84
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
NC – No internal connection
Uses Yamaichi socket IC51-1324-828
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SN74ABT3612
64 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
functional block diagram
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Mail1
Register
Parity
Gen/Check
RST
ODD/
EVEN
Device
Control
FFA
AFA
FS0
FS1
A0 – A35
EFA
AEA
36
64 × 36
SRAM
Write
Pointer
Read
Pointer
FIFO1
FIFO2
Status-Flag
Logic
Programmable-Flag
Offset Register
Status-Flag
Logic
Read
Pointer
Write
Pointer
MBF1
PEFB
PGB
36
EFB
AEB
B0 – B35
FFB
AFB
36
PGA
PEFA
MBF2
64 × 36
SRAM
Parity
Gen/Check
Mail2
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
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SN74ABT3612
64 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
Terminal Functions
PIN NAME I/O
A0 – A35
I/O
AEA
O
(port A)
AEB
O
(port B)
AFA
O
(port A)
O
AFB (port B)
B0 – B35
I/O
CLKA
I
CLKB
I
CSA
I
CSB
I
EFA
O
(port A)
EFB
O
(port B)
ENA
ENB
FFA
I
I
O
(port A)
FFB
O
(port B)
FS1, FS0
I
MBA
I
MBB
I
MBF1
O
DESCRIPTION
Port-A data. The 36-bit bidirectional data port for side A.
Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2
is less than or equal to the value in offset register X.
Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1
is less than or equal to the value in offset register X.
Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in
FIFO1 is less than or equal to the value in offset register X.
Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations in
FIFO2 is less than or equal to the value in offset register X.
Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA.
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0 – A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0 – B35 outputs are in the high-impedance state when CSB is high.
Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and
reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EFA is forced
low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty
FIFO2 memory.
Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and
reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is forced
low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty
FIFO1 memory.
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes
to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high
transition of CLKA after reset.
Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes
to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high
transition of CLKB after reset.
Flag-offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the almost-empty flag and almost-full flag offset.
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
A0 – A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIFO2 output register data for output.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0 – B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO1 output register data for output.
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and MBB is high. MBF1 is set high when the device is reset.
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5