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SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
D Member of the Texas Instruments
Widebus Family
D Advanced BiCMOS Technology
D Independent Asynchronous Inputs and
Outputs
D Two Separate 512 × 18 FIFOs Buffering
Data in Opposite Directions
D Programmable Almost-Full/Almost-Empty
Flags
D Empty, Full, and Half-Full Flags
D Fast Access Times of 12 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
D Supports Clock Rates up to 67 MHz
D Package Options Include 80-Pin Quad Flat
(PH) and 80-Pin Thin Quad Flat (PN)
Packages
PH PACKAGE
(TOP VIEW)
RSTA
PENA
AF/AEA
HFA
FULLA
GND
A0
A1
VCC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
VCC
A10
A11
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 64
2 63
3 62
4 61
5 60
6 59
7 58
8 57
9 56
10 55
11 54
12 53
13 52
14 51
15 50
16 49
17 48
18 47
19 46
20 45
21 44
22 43
23 42
24 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RSTB
PENB
AF/AEB
HFB
FULLB
GND
B0
B1
VCC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
VCC
B10
B11
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

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SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
PN PACKAGE
(TOP VIEW)
AF/AEA
HFA
FULLA
GND
A0
A1
VCC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
VCC
A10
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1 60
2 59
3 58
4 57
5 56
6 55
7 54
8 53
9 52
10 51
11 50
12 49
13 48
14 47
15 46
16 45
17 44
18 43
19 42
20 41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AF/AEB
HFB
FULLB
GND
B0
B1
VCC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
VCC
B10
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times. It
processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN74ABT7820 consists of bus-transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
(GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN74ABT7820.
The SN74ABT7820 is characterized for operation from 0°C to 70°C.
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SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
Bus A
Bus A
Bus A
Bus A
FIFO A
In Out
FIFO B
Out In
Bus B
Bus A
FIFO A
In Out
FIFO B
Out In
SAB SBA GAB GBA
L XHL
FIFO A
In Out
FIFO B
Out In
Bus B
Bus A
SAB SBA GAB GBA
XXLL
FIFO A
In Out
FIFO B
Out In
SAB SBA GAB GBA
X L LH
FIFO A
In Out
FIFO B
Out In
SAB SBA GAB GBA
HXHL
Bus B
Bus A
SAB SBA GAB GBA
H LHH
FIFO A
In Out
FIFO B
Out In
SAB SBA GAB GBA
L HHH
FIFO A
In Out
FIFO B
Out In
Bus B
Bus A
FIFO A
In Out
FIFO B
Out In
SAB SBA GAB GBA
XHLH
SAB SBA GAB GBA
HHHH
Figure 1. Bus-Management Functions
Bus B
Bus B
Bus B
Bus B
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
SELECT-MODE CONTROL TABLE
CONTROL
OPERATION
SBA SAB
A BUS
B BUS
L
L
Real-time B-to-A bus
Real-time A-to-B bus
HL
FIFO B-to-A bus
Real-time A-to-B bus
L H Real-time B-to-A bus
FIFO A-to-B bus
HH
FIFO B-to-A bus
FIFO A-to-B bus
OUTPUT-ENABLE CONTROL TABLE
CONTROL
OPERATION
GBA GAB
A BUS
B BUS
L L Isolation/input to A bus Isolation/input to B bus
HL
A bus enabled
Isolation/input to B bus
L H Isolation/input to A bus
B bus enabled
HH
A bus enabled
B bus enabled
Figure 1. Bus-Management Functions (Continued)
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logic symbol
SAB
SBA
GAB
GBA
RSTA
PENA
LDCKA
UNCKA
FULLA
EMPTYA
AF/AEA
HFA
66
79
65
80
1
2
77
69
5
70
3
4
SN74ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
Φ
FIFO
1
MODE
512 × 18 × 2
SN74ABT7820
0
EN1
EN2
RESET A
PROG ENA
LDCKA
RESET B
PROG ENB
LDCKB
UNCKA
FULLA
UNCKB
FULLB
EMPTYA
ALMOST FULL/
ALMOST EMPTY A
HALF-FULL A
EMPTYB
ALMOST FULL/
ALMOST EMPTY B
HALF-FULL B
64
RSTB
63
PENB
68
LDCKB
76
UNCKB
60
FULLB
75
EMPTYB
62
AF/AEB
61
HFB
7
A0
8
A1
10
A2
11
A3
13
A4
14
A5
16
A6
17
A7
19
A8
20
A9
22
A10
23
A11
25
A12
26
A13
28
A14
29
A15
31
A16
32
A17
0
A Data
17
0
B Data
17
58
B0
57
B1
55
B2
54
B3
52
B4
51
B5
49
B6
48
B7
46
B8
45
B9
43
B10
42
B11
40
B12
39
B13
37
B14
36
B15
34
B16
33
B17
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the PH package.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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