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SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
D 3-State Outputs Interface Directly With
System Bus
D Gated Output-Control LInes for Enabling or
Disabling the Outputs
D Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
– Parallel Load
– Do Nothing (Hold)
D For Application as Bus Buffer Registers
D Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
SN54173, SN54LS173A . . . J OR W PACKAGE
SN74173 . . . N PACKAGE
SN74LS173A . . . D or N PACKAGE
(TOP VIEW)
M
N
1Q
2Q
3Q
4Q
CLK
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLR
14 1D
13 2D
12 3D
11 4D
10 G2
9 G1
SN54LS173A . . . FK PACKAGE
(TOP VIEW)
TYPICAL
MAXIMUM
TYPE PROPAGATION
CLOCK
’173
’LS173A
DELAY TIME
23 ns
18 ns
FREQUENCY
35 MHz
50 MHz
3 2 1 20 19
1Q 4
18 1D
2Q 5
17 2D
NC 6
16 NC
description
3Q 7
15 3D
The ’173 and ’LS173A 4-bit registers include
4Q 8
14 4D
9 10 11 12 13
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or relatively low-impedance loads. The
high-impedance third state and increased
NC – No internal connection
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
CLR
H
L
L
L
L
CLK
X
L
FUNCTION TABLE
INPUTS
DATA ENABLE DATA
G1 G2 D
X XX
X XX
H XX
X HX
L LL
OUTPUT
Q
L
Q0
Q0
Q0
L
L
L
LH
H
When either M or N (or both) is (are) high, the output is
disabled to the high-impedance state; however, sequential
operation of the flip-flops is not affected.
logic symbol
CLR
M
N
G1
G2
CLK
15
1
2
9
10
7
14
1D
13
2D
12
3D
11
4D
’173
R
&
EN
&
C1
1D
3
1Q
4
2Q
5
3Q
6
4Q
CLR
M
N
G1
G2
CLK
15
1
2
9
10
7
14
1D
13
2D
12
3D
11
4D
’LS173A
R
&
EN
&
C1
1D
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
3
1Q
4
2Q
5
3Q
6
4Q
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logic diagram (positive logic)
Output
Control
1
M
2
N
14
1D
Data
Enable
G1 9
10
G2
13
2D
7
CLK
12
3D
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
1D
C1
R
1D
C1
R
1D
C1
R
3
1Q
4
2Q
5
3Q
11
4D
15
CLR
Pin numbers shown are for D, J, N, and W packages.
1D
C1
R
6
4Q
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
schematics of inputs and outputs
’173
Equivalent of Each Input
VCC
4 kNOM
’LS173A
Equivalent of Each Input
VCC
20 kNOM
Input
Input
Typical of All Outputs
VCC
90 NOM
Output
Typical of All Outputs
VCC
100 NOM
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage: ’173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
’LS173A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
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SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
recommended operating conditions (see Note 3)
SN54173
MIN NOM MAX
SN74173
UNIT
MIN NOM MAX
VCC Supply voltage
4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current
–2 –5.2 mA
IOL Low-level output current
16 16 mA
TA Operating free-air temperature
–55 125 0
70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54173
MIN TYP‡ MAX
SN74173
MIN TYP‡ MAX UNIT
VIH
VIL
VIK
VOH
High-level input voltage
Low-level input voltage
Input clamp voltage
High-level output voltage
VOL Low-level output voltage
IO(off)
Off-state (high-impedance state)
output current
II
Input current
at maximum input voltage
VCC = MIN,
VCC = MIN,
VIL = 0.8 V,
VCC = MIN,
VIL = 0.8 V,
VCC = MAX,
VIH = 2 V
VCC = MAX,
II = –12 mA
VIH = 2 V,
IOH = MAX
VIH = 2 V,
IOL = 16 mA
VO = 2.4 V
VO = 0.4 V
VI = 5.5 V
2
2.4
2
0.8
–1.5
2.4
0.4
150
–150
1
V
0.8 V
–1.5 V
V
0.4 V
40
µA
–40
1 mA
IIH High-level input current
VCC = MAX, VI = 2.4 V
40 40 µA
IIL Low-level input current
IOS Short-circuit output current§
VCC = MAX,
VCC = MAX
VI = 0.4 V
–30
–1.6
–70 –30
–1.6 mA
–70 mA
ICC Supply current
VCC = MAX, See Note 4
50 72
50 72 mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded;
and CLK and M at 4.5 V.
timing requirements over recommended operating conditions (unless otherwise noted)
fclock Input clock frequency
tw Pulse duration
tsu Setup time
th Hold time
CLK or CLR
Data enable (G1, G2)
Data
CLR (inactive state)
Data enable (G1, G2)
Data
SN54173
MIN MAX
25
20
17
10
10
2
10
SN74173
MIN MAX
25
20
17
10
10
2
10
UNIT
MHz
ns
ns
ns
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