Z16C30.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 Z16C30 데이타시트 다운로드

No Preview Available !

Z16C30
CMOS USC Universal
Serial Controller
Product Specification
DS007902-0708
PRELIMINARY
Copyright ©2008 by Zilog®, Inc. All rights reserved.
www.zilog.com

No Preview Available !

Warning: DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
DS007902-0708
PRELIMINARY

No Preview Available !

Z16C30
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
Date
July 2008
Jan 2000
Revision Level
02
Description
Updated as per latest template and
style guide.
01 Original issue
Page No
All
DS007902-0708
PRELIMINARY
Revision History

No Preview Available !

Z16C30
Product Specification
iv
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
USC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Communications Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Character Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Baud Rate Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Digital Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Block Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DS007902-0708
PRELIMINARY
Table of Contents

No Preview Available !

Z16C30
Product Specification
1
Architectural Overview
Features
The key features of Zilog’s Z16C30 device include:
Two Independent 0-to-10 Mbps Full-Duplex Channels, each with Two Baud Rate Gener-
ators and One digital phase-locked loop (DPLL) for Clock Recovery
32-byte Data FIFO’s for each Receiver and Transmitter
110 ns Bus Cycle Time, 16-bit Data Bus Bandwidth
Multi-Protocol Operation under Program Control with Independent Mode Selection for
Receiver and Transmitter
Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character in 1/16-bit Incre-
ments, Programmable Clock Factor, Break Detect and Generation, Odd, Even, Mark,
Space or no Parity and Framing Error Detection, Supports One Address/Data Bit and MIL
STD 1553B Protocols
Byte Oriented Synchronous Mode with One to Eight Bits/Character, Programmable Idle
Line Condition, Optional Receive Sync Stripping; Optional Preamble Transmission, 16-
or 32-bit CRC, and Transmit-to-Receive Slaving (for X.21)
Bisync Mode with 2- to 16-bit Programmable Sync Character, Programmable Idle Line
Condition, Optional Receive Sync Stripping, Optional Preamble Transmission, 16- or 32-
bit CRC
Transparent Bisync Mode with EBCDIC or ASCII Character Code, Automatic CRC Han-
dling, Programmable Idle Line Condition, Optional Preamble Transmission, Automatic
Recognition of DLE, SYN, SOH, ITX, ETX, ETB, EOT, ENQ, and ITB
External Character Sync Mode for Receive
HDLC/SDLC Mode with Eight-Bit Address Compare, Extended Address Field Option,
16- or 32-bit CRC, Programmable Idle Line Condition, Optional Preamble Transmission
and Loop Mode
DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmit-
ter
Channel Load Command for DMA Controlled Initialization
Flexible Bus Interface for Direct Connection to Most Microprocessors, User Programma-
ble for 8 or 16 Bits Wide, Directly Supports 680X0 Family or 8X86 Family Bus Interfaces
Low Power CMOS
68-Pin PLCC/100-Pin VQFP Packages
DS007902-0708
PRELIMINARY
Architectural Overview