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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z16C32 SL1660 ONLY
IUSCINTEGRATED UNIVERSAL
SERIAL CONTROLLER
1
GENERAL DESCRIPTION
The IUSC (Integrated Universal Serial Controller) is a sin-
gle-channel multple protocol data communications device
with on-chip dual-channel DMA. The integration of a high-
speed serial communications channel with a high perfor-
mance DMA facilitates higher data throughput than is pos-
sible with discrete serial/DMA chip combinations. The buff-
er chaining capabilities combined with features like
character counters, frame status block and buffer termina-
tion at the end of the frame facilitate sophisticated buffer
management that can significantly reduce CPU overhead.
The IUSC is software configurable to satisfy a wide variety
of serial communications applications. Offered at 20
Mbit/sec, its fast data transfer rate and multiple protocol
support make it ideal for applications in todays dynamic
environment of changing specifications and ever increas-
ing speed. The many programmable features allow the
user to tune the device response to meet system require-
ments and adapt to future changes with software instead
of redesigning hardware.
The on-chip DMA channels allow high-speed data trans-
fers for both the receiver and the transmitter. The device
supports automatic status transfer through DMA and al-
lows device initialization under DMA control. Each DMA
channel can transfer data words in as little as three 50 ns
clock cycles and can generate addresses compatible with
32-, 24- or 16-bit memory ranges. The DMA channels may
operate in any of four modes: single buffer, pipelined, ar-
ray-chained, or linked-list. The array-chained and linked-
list modes reduce the problems with segmentation and re-
assembly of messages in systems. To prevent the DMA
from holding bus mastership too long, mastership time
may be limited by counting the absolute number of clock
cycles, the number of bus transactions, or both.
The CPU bus interface is designed for use with any con-
ventional multiplexed or non-multiplexed bus. The device
contains a variety of sophisticated internal functions includ-
ing two baud rate generators, a digital phase-locked loop,
character counters, and 32-byte FIFOs for both the receiv-
er and transmitter.
The IUSC handles asynchronous formats, synchronous
byte-oriented formats (e.g., BISYNC), and synchronous
bit-oriented formats such as HDLC. This device supports
virtually any serial data transfer application.
The IUSC can generate, and check CRC in any synchro-
nous mode and is programmed to check data integrity in
various modes. Access to the CRC value allows system
software to resend or manipulate it as needed in various
applications. The IUSC also has facilities for modem con-
trols. In applications where these controls are not needed,
the modem controls can be used for general-purpose I/O.
Interrupts are supported by a daisy-chain hierarchy within
the serial channel and between the serial channel and the
DMA.
Support tools are available to aid the designer in efficiently
programming the IUSC. The Technical Manual describes
in detail all features presented in this Product Specification
and gives programming sequence hints. The EPMman-
ual (Electronic Programmers Manual) is an MS-DOS, disk-
based programming initialization tool, used in conjunction
with the Technical Manual. Also, there are assorted appli-
cation notes and development boards to assist the design-
er in hardware/software development.
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions
below:
Connection
Power
Ground
Circuit
VCC
GND
Device
VDD
VSS
CP97HHS0100
PRELIMINARY
1-1

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Z16C32 SL1660 ONLY
IUSCIntegrated Universal Serial Controller
.
Host
Processor
Bus
Interface
16-Bit Internal Data Bus
Transmit
DMA
Interrupt
Control
Transmit
FIFO
Time Slot
Assigner
Transmitter
Serial Clock
Logic
DPLL
Counters
BRG0, BRG1
Zilog
Receive
DMA
Receive
FIFO
Receiver
Time Slot
Assigner
I/O
Port
Figure 1. IUSC Block Diagram
1-2
PRELIMINARY
CP97HHS0100

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Zilog
/ABORT
/INT
IEI
IEO
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
/RxREQ
9
10
26
27
Z16C32 SL1660 ONLY
IUSCIntegrated Universal Serial Controller
1
1
PLCC 68 - Pin
61
60 /BIN
/BUSREQ
CLK
/BOUT
GND
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND
VCC
44 PORT 7
43
Figure 2. PLCC 68-Pin Assignments
CP97HHS0100
PRELIMINARY
1-3

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Z16C32 SL1660 ONLY
IUSCIntegrated Universal Serial Controller
Zilog
/UAS
/INTACK
R/W
/WR
/RD
/DS
/AS
VCC
VCC
NC
/RESET
/CS
D//C
S//D
/Wait//RDY
B//W
64
65
80
1
60
5
55 50
QFP 80 - Pin
10 15
45 41
40 PORT 6
PORT 5
PORT 4
PORT 3
PORT 2
PORT 1
PORT 0
GND
GND
/CTS
TxD
/TxC
/DCD
RxD
/RxC
25 /TxREQ
20 24
Figure 3. QFP 80-Pin Assignments
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PRELIMINARY
CP97HHS0100

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Zilog
Z16C32 SL1660 ONLY
IUSCIntegrated Universal Serial Controller
Address/
Data
Bus
Bus
Timing
Control
Interrupt
Ground
AD0
TxD
AD1
RxD
AD2
/TxC
AD3
/RxC
AD4
/CTS
AD5
/DCD
AD6 /RxREQ
AD7 /ABORT
AD8 /BUSREQ
AD9 /TxREQ
AD10
B//W
AD11
/UAS
AD12
/INT
AD13
IEI
AD14
IEO
AD15
PORT 0
/AS PORT 1
/DS Z16C32 PORT 2
/RD PORT 3
/WR
PORT 4
/CS PORT 5
S//D PORT 6
D//C
PORT 7
R//W
/BIN
/INTACK
/BOUT
/WAIT//RDY
CLK
/RESET
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Serial
Data
Channel
Clocks
Channel
I/O
Channel
DMA
Interface
Channel
Interrupt
I/O Port
System Clock
Device Reset
Power
Figure 4. Functional Diagram
1
CP97HHS0100
PRELIMINARY
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