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HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
7007L
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
◆ Low-power operation
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
◆ IDT7007 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆ M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in a 68-pin PLCC and a 80-pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/WL
15
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
15
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
1
Address
Decoder
CER
OER
R/WR
I/O0R-I/O7R
BUSYR(1,2)
A14R
A0R
SEMR
INTR(2)
2940 drw 01
SEPTEMBER 2019
DSC 2940/16

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7007L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
featurecontrolledby CEpermitstheon-chipcircuitryofeachporttoenter
a very LOW standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 850mW of power.
The IDT7007 is packaged in a 68-pin PLCC and an 80-pin thin
quad flatpack TQFP.
Pin Configurations(1,2,3)
I/O7R
N/C
OER
R/WR
SEMR
CER
A14R
A13R
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
27 9
28 8
29 7
30 6
31 5
32 4
33 3
34
7007
PLG68(4)
2
35 1
36
68-Pin PLCC
68
37
Top View
67
38 66
39 65
40 64
41 63
42 62
4344 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
A14L
A13L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
2940 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
2

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7007L
High-Speed 32K x 8 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
N/C
N/C
A6L
A7L
A8L
A9L
A10L
A11L
A12L
VCC
A13L
A14L
N/C
CEL
SEML
R/WL
OEL
N/C
I/O0L
I/O1L
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61 40
62 39
63 38
64 37
65 36
66 35
67 34
68 33
69
70
71
7007
PNG80(4)
32
31
30
72
80-Pin TQFP
29
73
74
Top View
28
27
75 26
76 25
77 24
78 23
79 22
80 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
N/C
N/C
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
GND
A13R
A14R
N/C
CER
SEMR
R/WR
OER
N/C
I/O7R
2940 drw 03
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
3

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7007L
High-Speed 32K x 8 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
51 50 48 46 44 42 40 38 36
11 A5L A4L A2L A0L BUSYL M/S INTR A1R A3R 11/06/01
53 52 49 47 45 43 41 39 37 35 34
10 A7L A6L A3L A1L INTL GND BUSYR A0R A2R A4R A5R
55 54
09 A9L A8L
32 33
A7R A6R
57 56
08 A11L A10L
30 31
A9R A8R
59 58
07 VCC A12L
61 60
06 A14L A13L
63 62
05 SEML CEL
IDT7007G
GU68(4)
68-Pin PGA
Top View(5)
28 29
A11R A10R
26 27
GND A12R
24 25
A14R A13R
65 64
04 OEL R/WL
22 23
SEMR CER
67 66
03 I/O0L N/C
20 21
OER R/WR
68 1 3 5 7 9 11 13 15 18 19
02 I/O1L I/O2L I/O4L GND I/O7L GND I/O1R VCC I/O4R I/O7R N/C
2 4 6 8 10 12 14 16 17
01 I/O3L I/O5L I/O6L VCC I/O0R I/O2R I/O3R I/O5R I/O6R
,
A BCDE
INDEX
NOTES:
1. All Vcc pins must be connected to power supply
2. All GND pins must be connected to ground.
3. Package body is approximately 1.8 in x 1.8 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
FG H JK L
2940 drw 04b
Pin Names
Left Port
Right Port
CEL CER
R/WL
R/WR
OEL OER
A0L - A14L
A0R - A14R
I/O0L - I/O7L
I/O0R - I/O7R
SEML
SEMR
INTL INTR
BUSYL
BUSYR
M/S
VCC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2940 tbl 01
4

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7007L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE R/W OE SEM I/O0-7
Mode
H X X H High-Z Deselected: Power-Down
L L X H DATAIN Write to Memory
L H L H DATAOUT Read Memory
X X H X High-Z Outputs Disabled
NOTE:
1. A0L — A14L ≠ A0R — A14R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
CE R/W OE SEM
I/O0-7
Mode
H H L L DATAOUT Read Semap hore Flag Data Out (I/O0-I/O7)
H ↑ X L DATAIN Write I/O0 into Semaphore Flag
L X X L ______ Not Allowed
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
2940 tbl 02
2940 tbl 03
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Military
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0
TBIAS
Temperature
Under Bias
-55 to +125 -65 to +135
TSTG Storage
Temperature
-65 to +150 -65 to +150
IOUT DC Output
Current
50 50
Unit
V
oC
oC
mA
Maximum Operating Temperature
and Supply Voltage(1)
Grade
Ambient
Temperature
GND
Vcc
Military
-55OC to+125OC
0V
5.0V + 10%
Commercial
0OC to +70OC
0V
5.0V + 10%
Industrial
-40OC to +85OC
0V
5.0V + 10%
NOTES:
2940 tbl 05
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
2940 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERMmustnotexceedVcc+10%formorethan25%ofthecycletimeor10nsmaximum,
and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max.
VCC Supply Voltage
4.5 5.0 5.5
GND Ground
0 00
Unit
V
V
Capacitance (TA = +25°C, f = 1.0Mhz)
Symbol
Parameter(1)
Conditions(2) Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT Output Capacitance
VOUT = 3dV
10 pF
VIH Input High Voltage
2.2 ____ 6.0(2) V
VIL Input Low Voltage
-0.5(1)
____
0.8
V
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
2940 tbl 06
NOTES:
2940 tbl 07
1. This parameter is determined by device characterization but is not production
tested. TQFP package only.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
5