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DATASHEET
X55060
64K Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FN8133
Rev 0.00
March 28, 2005
FEATURES
• Dual voltage monitoring
• Active high and active low reset outputs
• Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
—User programmable thresholds
• Lowline Output — Zero delayed POR
• Reset signal valid to VCC = 1V
• System battery switch-over circuitry
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect none(0), or all of EEPROM array with
programmable Block Lockprotection
—In circuit programmable ROM mode
BLOCK DIAGRAM
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 10MHz SPI interface modes (0,0 & 1,1)
• 2.7V to 5.5V power supply operation
• Available packages — 20-lead TSSOP
DESCRIPTION
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
V2MON
WP
SO
SI
SCK
CS
Watchdog Transition
Detector
Data
Register
Command
Decode, Test
& Control
Logic
V2 Monitor
Logic
+
V-TRIP2
VOUT
Protect Logic
Status
Register
EEPROM Array
512 X 128
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V2FAIL
WDO
RESET
BATT-ON
VOUT
VBATT
VCC
(V1MON)
System
Battery
Switch
VCCLoMgiocnitor
+
V-TRIP1
VOUT
Power-on,
Low Voltage
Reset
Generation
RESET/MR
LOWLINE
FN8133 Rev 0.00
March 28, 2005
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X55060
X55060
A system battery switch circuit compares VCC (V1MON)
with VBATT input and connects VOUT to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X55060
can drive 50mA from VCC and 250µA from VBATT. The
device switches to VBATT when VCC drops below the low
VCC voltage threshold and VBATT > VCC.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC (V1MON) falls below the minimum VCC
trip point (VTRIP1). RESET/RESET is asserted until VCC
returns to proper operating level and stabilizes. A second
voltage monitor circuit tracks the unregulated supply or
monitors a second power supply voltage to provide a
power fail warning. Intersil’s unique circuits allow the
threshold for either voltage monitor to be reprogrammed
to meet special needs or to fine-tune the threshold for
applications requiring higher precision.
ORDERING INFORMATION
X55060
Suffix
V20-4.5A
V20I-4.5A
V20-4.5
V20I-4.5
V20-2.7A
V20I-2.7A
V20-2.7
V20I-2.7
Vtrip1
4.6
4.6
2.9
2.6
Vtrip2
2.6
2.9
1.65
1.65
Temp Range
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
PIN CONFIGURATION
20-Pin TSSOP
CS/WDI
NC
SO
RESET
LOWLINE
V2FAIL
V2MON
WP
NC
VSS
1
2
3
4
5
6
7
8
9
10
20 VCC (V1MON)
19 WDO
18 RESET/MR
17 BATT-ON
16 VOUT
15 VBATT
14 SCK
13 NC
12 NC
11 SI
FN8133 Rev 0.00
March 28, 2005
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X55060
X55060
PIN DESCRIPTION
Pin Name
Function
1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET
going active.
2 NC No internal connections
3 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
4 RESET Reset Output. RESET is an active HIGH, open drain output which is the inverse of the RESET
output.
5 LOWLINE Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1 and
immediately goes HIGH when VCC > VTRIP1. This pin goes LOW 250ns before RESET pin.
6 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2
and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this
pin.
7 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC
when not used.
8 WP Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
9 NC No internal connections
10 VSS Ground
11 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
12 NC No internal connections
13 NC No internal connections
14
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
15 VBATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused connect
VBATT to ground.
FN8133 Rev 0.00
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X55060
X55060
PIN DESCRIPTION (CONTINUED)
Pin Name
Function
16
VOUT
Output Voltage. VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1, then,
VOUT = VCC if VCC > VBATT+0.03
VOUT = VBATT if VCC < VBATT-0.03
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
17 BATT-ON Battery On. This open drain output goes HIGH when the VOUT switches to VBATT and goes LOW
when VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to
the VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only
needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.
18 RESET Output/Manual Reset Input. This is an Input/Output pin.
/MR RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls
rbueplotewd.thReEmSiEnTimruemmaVinCsC
sense
active
level. When RESET is active communication to
until VCC rises above the minimum VCC sense
the device is inter-
level for 150ms.
RESET also goes active on power-up and remains active for 150ms after the power supply
stabilizes.
MR Input. This is an active LOW debounced input. When MR is active, the RESET/RESET pins
are asserted. When MR is released, the RESET/RESET remains asserted for tPURST, and then re-
leased.
19 WDO Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
20 VCC Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
(V1MON) voltage, RESET and RESET go ACTIVE.
PRINCIPLES OF OPERATION
Power-On Reset
Application of power to the X55060 activates a Power-
on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When VCC exceeds the device VTRIP1
value for 150ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin exe-
cuting code.
Low VCC (V1MON) Voltage Monitoring
During operation, the X55060 monitors the VCC level
and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP1. During this time the
communication to the device is interrupted. The
RESET/RESET signal also prevents the microproces-
sor from operating in a power fail or brownout condi-
tion. The RESET signal remains active until the
voltage drops below 1V. These also remain active until
VCC returns and exceeds VTRIP1 for tPURST.
Low V2MON Voltage Monitoring
The X55060 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. V2FAIL remains active until V2MON
returns and exceeds VTRIP2.
The V2MON voltage sensor is powered by VOUT. If
VCC and VBATT go away (i.e. VOUT goes away), then
V2MON cannot be monitored.
FN8133 Rev 0.00
March 28, 2005
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X55060
X55060
Figure 1. Two Uses of Dual Voltage Monitoring
Unregulated
Supply
R1
5V
Reg
R2 V2
VOUT
X55060
VCC
RESET
V2MON
V2FAIL
System
Reset
System
Interrupt
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
Unregulated
Supply
5V
Reg
3.3V
Reg
X55060
VCC RESET
V2MON
V2FAIL
VOUT
System
Reset
Notice: No external components required to monitor
two voltages.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS/WDI pin. The micropro-
cessor must toggle the CS/WDI pin HIGH to LOW
periodically prior to the expiration of the watchdog time
out period to prevent the WDO signal going active. The
state of two nonvolatile control bits in the Status Register
determines the watchdog timer period. The microproces-
sor can change these watchdog bits by writing to the sta-
tus register. The factory default setting disables the
watchdog timer.
The Watchdog Timer oscillator stops when in battery
backup mode. It re-starts when VCC returns.
System Battery Switch
As long as VCC exceeds the low voltage detect threshold
VTRIP1, VOUT is connected to VCC through a 5(typical)
switch. When the VCC has fallen below VTRIP, then VCC
is applied to VOUT if VCC is equal to or greater than
VBATT + 0.03V. When VCC drops to less than VBATT -
0.03V, then VOUT is connected to VBATT through an 80
(typical) switch. VOUT typically supplies the system static
RAM voltage, so the switchover circuit operates to pro-
tect the contents of the static RAM during a power fail-
ure. Typically, when VCC has failed, the SRAMs go into
a lower power state and draw much less current than in
their active mode. When VCC returns, VOUT switches
back to VCC when VCC exceeds VBATT + 0.03V. There is
a 60mV hysteresis around this battery switch threshold
to prevent oscillations between supplies.
While VCC is connected to VOUT the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Operation
The device is in normal operation with VCC as long as
VCC > VTRIP1. It switches to the battery backup mode
when VCC goes away.
Condition
VCC > VTRIP1
VCC > VTRIP1 &
VBATT = 0
0 VCC VTRIP1
and VCC < VBATT
Mode of Operation
Normal Operation.
Normal Operation without battery
back up capability.
Battery Backup Mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
FN8133 Rev 0.00
March 28, 2005
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