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HIGH-SPEED 128K x 8

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

709099L

Features

◆ True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆ High-speed clock to data access

– Industrial: 9ns (max.)

◆ Low-power operation

– IDT709099L

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

◆ Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

◆ Counter enable and reset features

◆ Dual chip enables allow for depth expansion without

additional logic

◆ Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 9ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 15ns cycle time, 66.7MHz operation in Pipelined output mode

◆ TTL- compatible, single 5V (±10%) power supply

◆ Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆ Available in a 100-pin Thin Quad Flatpack (TQFP) package

◆ Green parts available, see ordering information

Functional Block Diagram

R/WL

OEL

CE0L

CE1L

0/1

R/WR

OER

CE0R

1 CE1R

0/1

FT/PIPEL

I/O0L - I/O7L

A16L

A0L

CLKL

ADSL

CNTENL

CNTRSTL

0/1 1

I/O

Control

I/O

Control

0 1 0/1

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

FT/PIPER

I/O0R - I/O7R

A16R

A0R

CLKR

ADSR

CNTENR

CNTRSTR

4846 drw 01

AUGUST 2019

DSC-4846/10

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709099L

High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT709099 is a high-speed 128K x 8 bit synchronous Dual-

Port RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold

times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times.

With an input data register, the IDT709099 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.

An automatic power down feature, controlled by CE0 and CE1, permits

the on-chip circuitry of each port to enter a very low standby power

mode. Fabricated using CMOS high-performance technology, these

devices typically operate on only 1.2W of power.

Pin Configurations(1,2,3)

A6R

A5R

A4R

A3R

A2R

A1R

A0R

CNTENR

CLKR

ADSR

GND

ADSL

CLKL

CNTENL

A0L

A1L

A2L

A3L

A4L

A5L

A6L

7675 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5150

77 49

78 48

79 47

80 46

81 45

82 44

83 43

84 42

85 41

86 709099 40

87 PNG100(4) 39

88 38

89 100-PIN TQFP 37

90 TOP VIEW 36

91 35

92 34

93 33

94 32

95 31

96 30

97 29

98 28

99 27

100 26

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

I/O7R

I/O6R

I/O5R

I/O4R

I/O3R

VCC

I/O2R

I/O1R

I/O0R

GND

VCC

I/O0L

I/O1L

GND

I/O2L

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

GND

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm

4. This package code is used to reference the package diagram.

4846 drw 02

62.42

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709099L

High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM

Pin Names

Left Port

Right Port

Names

CE0L, CE1L

R/WL

OEL

A0L - A16L

I/O0L - I/O7L

CLKL

ADSL

CNTENL

CNTRSTL

FT/PIPEL

CE0R, CE1R

R/WR

OER

A0R - A16R

I/O0R - I/O7R

CLKR

ADSR

CNTENR

CNTRSTR

FT/PIPER

VCC

GND

Chip Enables

Read/Write Enable

Output Enable

Address

Data Input/Output

Clock

Address Strobe

Counter Enable

Counter Reset

Flow-Through/Pipeline

Power

Ground

4846 tbl 01

Industrial and Commercial Temperature Ranges

Truth Table I—Read/Write and Enable Control(1,2,3)

OE CLK CE0 CE1 R/W

I/O0-7

X↑HXX

High-Z

Deselected—Power Down

X↑X LX

High-Z

Deselected—Power Down

X↑LHL

DATAIN

Write

L ↑ L HH

DATAOUT

Read

HX L HX

High-Z

Outputs Disabled

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

Mode

4846 tbl 02

Truth Table II—Address Counter Control(1,2,6)

Address Address

Addr

Used

CLK ADS CNTEN CNTRST

I/O(3)

Mode

↑X

DI/O(0) Counter Reset to Address 0

An X An ↑ L(4) X H DI/O(n) External Address Utilized

An Ap Ap ↑ H H H DI/O(n) External Address Blocked—Counter Disabled (Ap reused)

Ap + 1

↑

L(5) H

DI/O(n+1) Counter Enable—Internal Address Generation

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE0 and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS is independent of all other signals including CE0 and CE1.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.

4846 tbl 03

6.342

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709099L

High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Grade

Ambient

Temperature(2)

GND

Vcc

Commercial

0OC to +70OC 0V 5.0V + 10%

Industrial

-40OC to +85OC

5.0V + 10%

NOTES:

4846 tbl 04

1. This is the parameter TA. This is the "instant on" case temperature.

Recommended DC Operating

Conditions

Symbol

Parameter

Min. Typ. Max. Unit

VCC Supply Voltage

4.5 5.0 5.5 V

GND Ground

0 0 0V

VIH Input High Voltage

2.2 ____ 6.0(1) V

VIL Input Low Voltage

-0.5(2)

____

0.8

NOTES:

1. VTERM must not exceed Vcc + 10%.

2. VIL > -1.5V for pulse width less than 10ns.

4846 tbl 05

Absolute Maximum Ratings(1)

Symbol

Rating

Commercial

& Industrial

Unit

VTERM(2)

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

TBIAS

Temperature

Under Bias

-55 to +125

TSTG Storage

Temperature

-65 to +150

IOUT DC Output

Current

50 mA

NOTES:

4846 tbl 06

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

Capacitance(1)

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter

Conditions(2)

Max. Unit

CIN Input Capacitance

VIN = 3dV

9 pF

COUT(3) Output Capacitance

VOUT = 3dV

10 pF

NOTES:

4846 tbl 07

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch from

0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range (VCC = 5.0V ± 10%)

Symbol

|ILI|

|ILO|

VOL

VOH

Parameter

Input Leakage Current(1)

Output Leakage Current

Output Low Voltage

Output High Voltage

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

Test Conditions

VCC = 5.5V, VIN = 0V to VCC

CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC

IOL = +4mA

IOH = -4mA

709099L

Min. Max.

___ 5

___ 0.4

2.4 ___

Unit

µA

4846 tbl 08

64.42

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709099L

High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)

709099L9

Com'l

& Ind

709099L12

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.(4) Max. Typ.(4) Max. Unit

ICC Dynamic Operating

Current

(Both Ports Active)

CEL and CER= VIL

Outputs Disabled

f = fMAX(1)

COM'L L

250

400

230

355 mA

IND

L 300 430 ____

____

ISB1 Standby Current

(Both Ports - TTL

Level Inputs)

CEL = CER = VIH

f = fMAX(1)

COM'L

IND

135 70

160

____

110 mA

____

ISB2 Standby Current

(One Port - TTL

Level Inputs)

CE"A" = VIL and

CE"B" = VIH(3)

Active Port Outputs

Disabled, f=fMAX(1)

COM'L L

175

275

150

240 mA

IND

L 195 295 ____

____

ISB3 Full Standby Current

(Both Ports -

CMOS Level Inputs)

Both Ports CER and

CEL > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < 0.2V, f = 0(2)

COM'L L

0.5

3.0

0.5

3.0 mA

IND

L 0.5 6.0 ____ ____

ISB4 Full Standby Current

CE"A" < 0.2V and

COM'L L

170

270

140

225 mA

(One Port -

CE"B" > VCC - 0.2V(5)

CMOS Level Inputs)

VIN > VCC - 0.2V or

IND L

____

VIN < 0.2V, Active Port

190 290

Outputs Disabled, f = fMAX(1)

NOTES:

4846 tbl 09

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

6.542