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10-Quad
RapidIO® Switch
Datasheet
80KSW0005
1 Device Overview
The CPS-10Q (80KSW0005) is a serial RapidIO switch whose functionality is
central to routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other sRIO-based devices. The CPS-10Q supports serial
RapidIO packet switching (unicast, multicast, and an optional broadcast) from
any of its 16 input ports to any of its 16 output ports.
2 Features
u Interfaces - sRIO
40 bidirectional serial RapidIO (sRIO) lanes v 1.3
Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps
All lanes support short haul or long haul reach for each PHY speed
Configurable port count to up to 16 ports
Two enhanced quads can be configured as 4 1x ports or 1 4x ports
Supports standard 4 levels of priority
Error handling support: It allows error detection, logging and
response from all major functional blocks on the device.
u Interfaces - I2C
Provides I2C port for maintenance and error reporting
Master or Slave Operation
Master allows power-on configuration from external ROM
Master mode configuration with external image compressing and
checksum
u Performance
100 Gbps of peak switching bandwidth
Non-blocking data flow architecture within each sRIO priority
low latency for all packet length and load condition
Internal queuing buffer and retransmit buffer
Standard receiver based physical layer flow control
u Features
Configurable for cut-thru and store-and-forward
Device configurable through any of sRIO ports,
Im2Co,doersJTAG
Packet Trace function: It allows copying or filtering packets on a per-
port basis. Each port provides the ability to match the first 160 bits of
any packet against up to 4 programmable comparison values to copy
the packet to a programmable output trace port or drop it.
Supports up to 40 simultaneous multicast masks per each port
Support Broadcast
Port Loopback Debug Feature
Software assisted error recovery, supporting hot swap
Ports may be individually turned off to reduce power
PMON counters for monitor and diagnostics per port
Serdes physical diagnostic registers
Embedded PRBS generation and detection with programmable poly-
nomial cover error rate under all conditions
0.13um technology
Low power dissipation
Full JTAG Boundary Scan support (IEEE1149.1 & 1149.6)
Package: FCBGA 676-ball grid array, 27mm x 27mm, 1.0mm ball
pitch
3 Block Diagram
Ln0
Ln1
Ln2
Ln3
Ln4
Ln5
Ln6
Ln7
Ln8
Ln9
Ln10
Ln11
Ln12
Ln13
Ln14
Ln15
Ln16
Ln17
Ln18
Ln19
sRIO Q0
Standard
(1 port)
sRIO Q1
Standard
(1 port)
sRIO Q2
Standard
(1 port)
sRIO Q3
Standard
(1 port)
sRIO Q4
Enhanced
(1 or 4 ports)
2010 Integrated Device Technology, Inc. All rights reserved.
Serial RapidIO Switch
CPS-10Q
Maintenance
&
Error
Management
JTAG
Configuration
Figure 1 Block diagram
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I2C
sRIO Q9
Enhanced
(1 or 4 ports)
sRIO Q8
Standard
(1 port)
sRIO Q7
Standard
(1 port)
sRIO Q6
Standard
(1 port)
sRIO Q5
Standard
(1 port)
Ln39
Ln38
Ln37
Ln36
Ln35
Ln34
Ln33
Ln32
Ln31
Ln30
Ln29
Ln28
Ln27
Ln26
Ln25
Ln24
Ln23
Ln22
Ln21
Ln20
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CPS-10Q
CPS-10Q Datasheet
4 Device Description
The CPS-10Q is optimized for cost-effective high performance RapidIO switching, typically used in embedded applications. Typical applications
include backplane switching and intensive signal processing where the switch is key to switching on the data path. These applications include wireless
infrastructure base station and RNCs, radar and sonar, and medical imaging. It can serve equally as backplane or linecard switch, supporting up to 16
ports. It is an end-point free (switch) device in an sRIO network.
The CPS-10Q receives packets from up to 16 ports. The device offers full support for normal switching as well as enhanced functions:
1) Normal Switching: All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determining
how the packet is routed.
Three major options exist within this category:
a. Multicast: If a Multicast ID is received, the CPS-10Q performs a multicast as defined in the sRIO multicast registers.
b. Unicast: specified by sRIO.
c. Maintenance packets: As specified by sRIO.
The CPS-10Q supports a peak throughput of 100 Gbps which is the line rate for 10 ports in 4x configuration, each at 10 Gbps (3.125 Gbps minus the
sRIO-defined 8b/10b encoding), and switches dynamically in accordance with the packet headers and priorities.
2) Enhanced functions
Enhanced features are provided for support of system debug. These features which are optional for the user consist of two major functions:
a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incom-
ing packet against user-defined comparison register values. The trace feature is available on all serial RapidIO ports, each acting indepen-
dently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to 4
comparison registers. In the event of a match, either of two possible user defined actions may take place:
i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent to
a “trace port.” The trace port itself may be any of the standard serial RapidIO ports. The port used for the trace port is defined by the user
through simple register configuration.
ii) the packet is dropped.
If there is no match, the packets route normally through the switch with no action taken.
The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It might
be used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identi-
fied (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level.
b. Port Loopback: The CPS-10Q offers internal loopback for each port that may be used for system debug of the high speed sRIO ports. By
enabling loopback on a given port, packets sent to the port’s receiver are immediately looped back at the physical layer to the transmitter -
bypassing the higher logical or transport layers.
c. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports of that multicast operation.
The CPS-10Q can be programmed through any one or combination of sRIO, I2C, or JTAG. Note that any sRIO port may be used for programming.
The device can also configure itself on power-up by reading directly from ROM over I2C in master mode.
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CPS-10Q
5 Applications
Central switch baseband system wireless processing
CPS-10Q Datasheet
RF Card (RE)
RF TDM
Receiver
Baseband System (REC) -RapidIO Based
CPRI
sRIO
FPGA
sRIO
80HFC1001
CPRI FIC
80HFC1000
CPRI FIC
CCPPSS-1- 100QQ
CPS- 6Q
DSP
RF Card (RE)
RF TDM
Receiver
80HFC1001
CPRI FIC
80KSBR201
Serial Buffer
DSP
DSP
Figure 1 Application Overview
Note: The CPS-10Q provides direct support for backplane connections using the serial RapidIO standard. The addition of an appropriate bridge (e.g.,
CPRI sRIO) allows for further backplane flexibility, accommodating designs based on a wide range of standards such as CPRI, OBSAI, GbE or
PCIe.
In a macro wireless station, a switch-based raw data combination and distribution architecture is widely adopted. Switch based architecture provides
high flexibility and high resource efficiency. The raw data from the Radio Unit is distributed to one or more processing cards by unicast or multicast.
Aggregating raw data from processing cards to a buffer-less chain can be done by a fast non-blocking switch.
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CPS-10Q
Media Gateway and general processing
CPS-10Q Datasheet
Figure 2 Application Overview
Note: The CPS-10Q provides direct support for backplane connections using the serial RapidIO standard.
A low jitter switch enables fully DSP processing power. Priority support, fast switching, and multicasting will differentiate class of traffic to provide QoS.
6 Functional Overview
The CPS-10Q is optimized for either board-level DSP/ASIC cluster applications or module-level distributed processing application. Up to 16 serial
RapidIO ports fully meet standard v1.3. The physical lanes may be configured to operate at 3.125Gbps, 2.5Gbps or 1.25Gbps. All lanes independently
work in short haul or long haul. The switch has a sustained 80Gbps bandwidth. It is non-blocking within a given sRIO priority.
The CPS-10Q can be programmed through a CPU or a DSP connected to one of the sRIO ports of the device or with a CPU connected to an I2C or
JTAG bus, it can also work along with a I2C configuration memory. This option allows the device work in “remote stand alone” mode.
Each sRIO port provides a packet trace capability. For any packet received by a port, a comparison between the first 160 bits and up to four configu-
rable values can be performed. A match against any of these parameters will result in a copy of the packet and a route of the packet to a configurable
ouput port. This feature can be used as a tactical function to track user data or in a debug environment to test how specific packets are moving
through the platform.
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CPS-10Q
7 Interfaces Overview
CPS-10Q Datasheet
Rext
40
Differential
sRIO Lanes
1.25, 2.5, or
3.125 Gbps
I2C
Interface
400KHz
IDT CPS-10Q
RST
REF_CLK
SPD[1:0]
IRQ
Figure 3 Interface Diagram
sRIO Ports
The sRIO interfaces are the main communication ports on the switch. These ports are compliant with the serial RapidIO v. 1.3 specifications. Please
refer to the serial RapidIO specifications for full detail [2-10].
The CPS-10Q provides 40 differential dual simplex transceivers dedicated to sRIO I/O. In addition to standard quads that act as a single 1x or 4x port,
two enhanced quads can be independently configured to run in various configurations as 4 1x-ports or 1 4x-ports. The device supports a maximum of
16 1x-ports, or 10 4x-ports. Each port can be programmed to run independently at 1.25, 2.5, or 3.125Gbps. Each lane is able to handle long- or short-
haul serial transmission per RIO serial spec.
In the CPS-10Q there are 8 “Standard Quads” which follow the standard sRIO physical interface implementation. These ports either operate in 4x-
mode or as a single 1x-port. For example Lanes 0 - 3 are programmable into one 4x- or one 1x-port. Per sRIO standard, either the 1st or 3rd lanes in
a given 4x group may be used as a valid link for a 1x port. For example, either lane 0 or lane 2 may be connected in support of a 1x-port.
The CPS-10Q also has a proprietary implementation which we refer to as an “Enhanced Quad” for Quad4 and Quad9. An Enhanced Quad can be
operated in standard sRIO mode like the standard quads. Additionally the Enhanced Quad can be register-configured to run as 4 independent 1x-
ports. In this manner, the user has the flexibility to use one, multiple, or two lanes in 1x-mode. For example, lanes 16 - 19 of the CPS-10Q are
programmable into one 4x- or four 1x-ports. This is unlike the standard sRIO port implementation that, when configured as a 1x-port, renders the
remaining possible connections unused.
I2C Bus
This interface may be used as an alternative to the standard sRIO or JTAG ports to program the switch and to check the status of registers - including
the error reporting registers. It is fully compliant with the I2C specification, it supports master mode and slave mode, also supports both Fast- and
Slow-mode buses [1]. Refer to the “I2C” section for full detail.
JTAG TAP Port
This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I2C
ports to program the switch and to check the status of registers - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full
detail.
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