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FEATURES
Monolithic 14-Bit, 3 MSPS A/D Converter
Low Power Dissipation: 110 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 79.0 dB
Spurious-Free Dynamic Range: 91.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Lead MQFP
Complete 14-Bit, 3.0 MSPS
Monolithic A/D Converter
AD9243
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DVDD DRVDD
VINA
VINB
CML
CAPT
CAPB
VREF
SENSE
SHA
MDAC1
GAIN = 16
5
A/D
5
MDAC2
GAIN = 8
MDAC3
GAIN = 8
4
A/D
4
A/D
44
DIGITAL CORRECTION LOGIC
14
OUTPUT BUFFERS
A/D
4
MODE
SELECT
1V
AD9243
REFCOM
AVSS
DVSS DRVSS
OTR
BIT 1
(MSB)
BIT 14
(LSB)
PRODUCT DESCRIPTION
The AD9243 is a 3 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9243 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9243 performs well in communication systems employ-
ing Direct-IF Down Conversion since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 1.5 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9243 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-lead Metric Quad
Flatpack.
Low Power and Single Supply
The AD9243 consumes only 110 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9243 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9243 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998

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AD9243* Product Page Quick Links
Last Content Update: 08/30/2016
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Documentation
Application Notes
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9243: Complete 14-Bit, 3 MSPS Monolithic A/D
Converter Data Sheet
Tools and Simulations
• Visual Analog
Reference Materials
Analog Dialogue
• 14-Bit Monolithic ADCs: First to Sample Faster than 1
MSPS
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources
• AD9243 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9243 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

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AD9243–SPECIFICATIONS
DC SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, fSAMPLE = 3 MSPS, VREF = 2.5 V, VINB = 2.5 V, TMIN to TMAX unless
otherwise noted)
Parameter
AD9243
Units
RESOLUTION
14 Bits min
MAX CONVERSION RATE
INPUT REFERRED NOISE
VREF = 1 V
VREF = 2.5 V
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL1
DNL1
No Missing Codes
Zero Error (@ +25°C)
Gain Error (@ +25°C)2
Gain Error (@ +25°C)3
TEMPERATURE DRIFT
Zero Error
Gain Error2
Gain Error3
POWER SUPPLY REJECTION
3 MHz min
0.9 LSB rms typ
0.36 LSB rms typ
± 2.5 LSB typ
± 0.6 LSB typ
± 1.0 LSB max
± 2.5 LSB typ
± 0.7 LSB typ
14 Bits Guaranteed
0.3 % FSR max
1.5 % FSR max
0.75 % FSR max
3.0 ppm/°C typ
20.0 ppm/°C typ
5.0 ppm/°C typ
0.1 % FSR max
ANALOG INPUT
Input Span (with VREF = 1.0 V)
Input Span (with VREF = 2.5 V)
Input (VINA or VINB) Range
Input Capacitance
2
5
0
AVDD
16
V p-p min
V p-p max
V min
V max
pF typ
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.5 V Mode)
Output Voltage Tolerance (2.5 V Mode)
Load Regulation4
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DVDD
DRVDD
Supply Current
IAVDD
IDRVDD
IDVDD
1
± 14
2.5
± 35
2.0
5
+5
+5
+5
23.0
1.0
5.0
Volts typ
mV max
Volts typ
mV max
mV max
ktyp
V (± 5% AVDD Operating)
V (± 5% DVDD Operating)
V (± 5% DRVDD Operating)
mA max (20 mA typ)
mA max (0.5 mA typ)
mA max (3.5 mA typ)
POWER CONSUMPTION
110 mW typ
145 mW max
NOTES
1VREF =1 V.
2Including internal reference.
3Excluding internal reference.
4Load regulation with 1 mA load current (in addition to that required by the AD9243).
Specification subject to change without notice.
–2– REV. A

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AD9243
AC SPECIFICATIONS (AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, fSAMPLE = 3 MSPS, VREF = 2.5 V, AIN = –0.5 dBFS, AC Coupled/
Differential Input, TMIN to TMAX unless otherwise noted)
Parameter
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
fINPUT = 500 kHz
fINPUT = 1.5 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 500 kHz
fINPUT = 1.5 MHz
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 500 kHz
fINPUT = 1.5 MHz
TOTAL HARMONIC DISTORTION (THD)
fINPUT = 500 kHz
fINPUT = 1.5 MHz
SPURIOUS FREE DYNAMIC RANGE
fINPUT = 500 kHz
fINPUT = 1.5 MHz
DYNAMIC PERFORMANCE
Full Power Bandwidth
Small Signal Bandwidth
Aperture Delay
Aperture Jitter
Acquisition to Full-Scale Step (0.0025%)
Overvoltage Recovery Time
Specifications subject to change without notice.
AD9243
75.0
79.0
77.0
12.3
12.8
12.5
76.0
80.0
79.0
–78.0
–87.0
–82.0
91.0
84.0
40
40
1
4
80
167
Units
dB min
dB typ
dB typ
Bits min
Bits typ
Bits typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
dB typ
MHz typ
MHz typ
ns typ
ps rms typ
ns typ
ns typ
DIGITAL SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)
Parameters
Symbol
AD9243
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = DVDD)
Low Level Input Current (VIN = 0 V)
Input Capacitance
LOGIC OUTPUTS (with DRVDD = 5 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA)
Output Capacitance
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA)
Low Level Output Voltage (IOL = 50 µA)
Specifications subject to change without notice.
VIH
VIL
IIH
IIL
CIN
VOH
VOH
VOL
VOL
COUT
VOH
VOL
+3.5
+1.0
± 10
± 10
5
+4.5
+2.4
+0.4
+0.1
5
+2.4
+0.7
Units
V min
V max
µA max
µA max
pF typ
V min
V min
V max
V max
pF typ
V min
V max
REV. A
–3–

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AD9243
SWITCHING SPECIFICATIONS (TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, CL = 20 pF)
Parameters
Clock Period1
CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay (Latency)
Symbol
tC
tCH
tCL
tOD
AD9243
333
150
150
8
13
19
3
Units
ns min
ns min
ns min
ns min
ns typ
ns max
Clock Cycles
NOTES
1The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.
ANALOG
INPUT
INPUT
CLOCK
DATA
OUTPUT
S1 S2
tC
tCH tCL
S3
S4
Figure 1. Timing Diagram
tOD
DATA 1
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
to Min
Max
Units
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFP
θJA = 53.2°C/W
θJC = 19°C/W
ORDERING GUIDE
Model
Temperature
Range
AD9243AS –40°C to +85°C
AD9243EB Evaluation Board
*S = Metric Quad Flatpack.
Package
Description
44-Lead MQFP
Package
Option*
S-44
AVDD
AVSS –0.3 +6.5
V
DVDD
DVSS –0.3 +6.5
V
AVSS
DVSS –0.3 +0.3
V
AVDD
DVDD –6.5 +6.5
V
DRVDD
DRVSS –0.3 +6.5
V
DRVSS
AVSS –0.3 +0.3
V
REFCOM
AVSS –0.3 +0.3
V
CLK
DVSS –0.3 DVDD + 0.3 V
Digital Outputs
DRVSS –0.3 DRVDD + 0.3 V
VINA, VINB
AVSS –0.3 AVDD + 0.3 V
VREF
AVSS –0.3 AVDD + 0.3 V
SENSE
AVSS –0.3 AVDD + 0.3 V
CAPB, CAPT
AVSS –0.3 AVDD + 0.3 V
Junction Temperature
+150
°C
Storage Temperature
–65 +150
°C
Lead Temperature
(10 sec)
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
PIN CONNECTIONS
44 43 42 41 40 39 38 37 36 35 34
DVSS 1
AVSS 2
DVDD 3
AVDD 4
DRVSS 5
DRVDD 6
CLK 7
NC 8
NC 9
NC 10
(LSB) BIT 14 11
PIN 1
IDENTIFIER
AD9243
TOP VIEW
(Not to Scale)
33 REFCOM
32 VREF
31 SENSE
30 NC
29 AVSS
28 AVDD
27 NC
26 NC
25 OTR
24 BIT 1 (MSB)
23 BIT 2
12 13 14 15 16 17 18 19 20 21 22
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9243 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A