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a
Complete 8-Bit, 32 MSPS, 95 mW
CMOS A/D Converter
AD9280
FEATURES
CMOS 8-Bit 32 MSPS Sampling A/D Converter
Pin-Compatible with AD876-8
Power Dissipation: 95 mW (3 V Supply)
Operation Between +2.7 V and +5.5 V Supply
Differential Nonlinearity: 0.2 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
PRODUCT DESCRIPTION
The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9280 uses a multistage
differential pipeline architecture at 32 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the AD9280 has been designed to ease the devel-
opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
The sample-and-hold amplifier (SHA) is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and beyond the Nyquist rate. AC-coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit. The dynamic performance is excellent.
The AD9280 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9280 can operate with a supply range from +2.7 V to
+5.5 V, ideally suiting it for low power operation in high speed
applications.
The AD9280 is specified over the industrial (–40°C to +85°C)
temperature range.
PRODUCT HIGHLIGHTS
Low Power
The AD9280 consumes 95 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.
Very Small Package
The AD9280 is available in a 28-lead SSOP package.
Pin Compatible with AD876-8
The AD9280 is pin compatible with the AD876-8, allowing
older designs to migrate to lower supply voltages.
300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either single-
ended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9280’s input range.
Built-In Clamp Function
Allows dc restoration of video signals.
FUNCTIONAL BLOCK DIAGRAM
CLAMP
CLAMP IN
CLK
AVDD
DRVDD
VINA
REFTF
REFTS
REFBS
REFBF
VREF
REFSENSE
SHA SHA GAIN
SHA GAIN SHA
GAIN
SHA
GAIN
A/D
A/D D/A
A/D D/A
A/D D/A
A/D D/A
CORRECTION LOGIC
1V AD9280
OUTPUT BUFFERS
AVSS
DRVSS
STBY
MODE
THREE-
STATE
OTR
D7 (MSB)
D0 (LSB)
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2010

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AD9280* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Documentation
Application Notes
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9280: Complete 8-bit, 32 MSPS, 95 mW CMOS A/D
Converter Data Sheet
Tools and Simulations
• Visual Analog
Reference Materials
Technical Articles
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources
• AD9280 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9280 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

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AD9280–SPECIFICATIONS (AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted)
Parameter
Symbol Min Typ Max
Units Condition
RESOLUTION
8 Bits
CONVERSION RATE
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Gain Error
REFERENCE VOLTAGES
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
Reference Input Resistance1
FS 32 MHz
DNL
INL
EZS
EFS
± 0.2 ± 1.0
± 0.3 ± 1.5
± 0.2 ± 1.8
± 1.2 ± 3.9
LSB
LSB
% FSR
% FSR
REFTS = 2.5 V, REFBS = 0.5 V
REFTS
REFBS
1
GND
2
10
4.2
AVDD V
AVDD – 1 V
V p-p
k
k
REFTS, REFBS: MODE = AVDD
Between REFTF & REFBF: MODE = AVSS
ANALOG INPUT
Input Voltage Range
Input Capacitance
Aperture Delay
Aperture Uncertainty (Jitter)
Input Bandwidth (–3 dB)
Full Power (0 dB)
DC Leakage Current
AIN
REFBS
REFTS V
REFBS Min = GND: REFTS Max = AVDD
CIN 1
tAP 4
tAJ 2
BW
pF Switched
ns
ps
300 MHz
43 µA Input = ± FS
INTERNAL REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2 V Mode)
Load Regulation (1 V Mode)
VREF
VREF
1
± 10 ± 25
2
0.5 2
V REFSENSE = VREF
mV
V REFSENSE = GND
mV 1 mA Load Current
POWER SUPPLY
Operating Voltage
Supply Current
Power Consumption
Power-Down
Gain Error Power Supply Rejection
AVDD
DRVDD
IAVDD
PD
2.7
2.7
PSRR
3 5.5
3 5.5
31.7 36.7
95 110
4
1
V
V
mA
mW
mW
% FS
AVDD = 3 V, MODE = AVSS
AVDD = DRVDD = 3 V, MODE = AVSS
STBY = AVDD, MODE and CLOCK
= AVSS
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
Signal-to-Noise and Distortion
SINAD
f = 3.58 MHz
f = 16 MHz
Effective Bits
f = 3.58 MHz
f = 16 MHz
Signal-to-Noise
SNR
f = 3.58 MHz
f = 16 MHz
Total Harmonic Distortion
THD
f = 3.58 MHz
f = 16 MHz
Spurious Free Dynamic Range
SFDR
f = 3.58 MHz
f = 16 MHz
Differential Phase
DP
Differential Gain
DG
46.4 49
48
7.8
7.7
47.8 49
48
–62 –49.5
–58
66 51.4
61
0.2
0.08
dB
dB
Bits
Bits
dB
dB
dB
dB
dB
dB
Degree
%
NTSC 40 IRE Mod Ramp
–2– REV. E

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AD9280
Parameter
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
DIGITAL OUTPUTS
High-Z Leakage
Data Valid Delay
Data Enable Delay
Data High-Z Delay
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA)
LOGIC OUTPUT (with DRVDD = 5 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA)
CLOCKING
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
CLAMP
Clamp Error Voltage
Clamp Pulsewidth
NOTES
1See Figures 1a and 1b.
Specifications subject to change without notice.
Symbol Min Typ Max Units Condition
VIH 2.4
VIL
V
0.3 V
IOZ –10
+10 µA
Output = GND to VDD
tOD 25 ns CL = 20 pF
tDEN
25 ns
tDHZ
13 ns
VOH +2.95
VOH +2.80
VOL
VOL
+0.4
+0.05
V
V
V
V
VOH +4.5
VOH +2.4
VOL
VOL
V
V
+0.4 V
+0.1 V
tCH 14.7
tCL 14.7
3
ns
ns
Cycles
EOC
± 60 ± 80 mV
CLAMPIN = +0.5 V to +2.0 V,
RIN = 10
tCPW 2 µs CIN = 1 µF (Period = 63.5 µs)
10k
REFTS
10k
REFBS
MODE
AVDD
AD9280
0.4 ؋ VDD
REFTS
REFTF
REFBF
REFBS
MODE
a.
Figure 1. Equivalent Input Load
AD9280
4.2k
b.
REV. E
–3–

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AD9280
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
to Min
Max
Units
AVDD
AVSS
DRVDD
DRVSS
AVSS
DRVSS
AVDD
DRVDD
MODE
AVSS
CLK
AVSS
Digital Outputs DRVSS
AIN AVSS
VREF
AVSS
REFSENSE
AVSS
REFTF, REFTB AVSS
REFTS, REFBS AVSS
Junction Temperature
Storage Temperature
Lead Temperature
10 sec
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
+6.5 V
+6.5 V
+0.3 V
+6.5 V
AVDD + 0.3 V
AVDD + 0.3 V
DRVDD + 0.3 V
AVDD + 0.3 V
AVDD + 0.3 V
AVDD + 0.3 V
AVDD + 0.3 V
AVDD + 0.3 V
+150
°C
+150
°C
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
AVDD
DRVDD
AVDD
AVDD
AVDD
AVDD
AVSS
DRVSS
DRVSS
a. D0–D7, OTR
AVDD
AVSS
d. AIN
AVDD
AVSS
AVSS
AVSS
AVSS
b. Three-State, Standby, Clamp
c. CLK
AVDD
REFBS 25
AVSS
AVDD
REFBF 24
AVSS
AVDD
REFTF 22
AVSS
AVDD
REFTS 21
AVSS
e. Reference
AVDD
AVDD
AVDD
AVSS
f. CLAMPIN
AVSS
AVSS
g. MODE
h. REFSENSE
Figure 2. Equivalent Circuits
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9280 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
AVSS
i. VREF
WARNING!
ESD SENSITIVE DEVICE
REV. E