AD9410.pdf 데이터시트 (총 21 페이지) - 파일 다운로드 AD9410 데이타시트 다운로드

No Preview Available !

FEATURES
SNR = 54 dB with 99 MHz analog input
500 MHz analog bandwidth
On-chip reference and track and hold
1.5 V p-p differential analog input range
5.0 V and 3.3 V supply operation
3.3 V CMOS/TTL outputs
Power: 2.1 W typical at 210 MSPS
Demultiplexed outputs each at 105 MSPS
Output data format option
Data sync input and data clock output provided
Interleaved or parallel data output option
APPLICATIONS
Communications and radars
Local multipoint distribution services (LMDS)
High-end imaging systems and projectors
Cable reverse paths
Point-to-point radio links
GENERAL DESCRIPTION
The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
optimized for high speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.
The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL-/CMOS-compatible and
separate output power supply pins also support interfacing with
3.3 V logic.
The clock input is differential and TTL-/CMOS-compatible.
The 10-bit digital outputs can be operated from 3.3 V (2.5 V to
3.6 V) supplies. Two output buses support demultiplexed data
up to 105 MSPS rates and binary or twos complement output
coding format is available. A data sync function is provided for
timing-dependent applications. An output clock simplifies
interfacing to external logic. The output data bus timing is
selectable for parallel or interleaved mode, allowing for
flexibility in latching output data.
10-Bit,
210 MSPS ADC
AD9410
AIN
AIN
DS
DS
CLK+
CLK–
FUNCTIONAL BLOCK DIAGRAM
REFIN REFOUT AGND DGND VD VDD VCC
REFERENCE
ADC
T/H 10-BIT
CORE
TIMING AND
SYNCHRONIZATION
AD9410
PORT 10
A
10
PORT 10
B
DFS
I/P
Figure 1.
ORA
DA9–DA0
ORB
DB9–DB0
DCO
DCO
Fabricated on an advanced BiCMOS process, the AD9410 is
available in an 80-lead thin quad flat package, exposed pad
specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Resolution at High Speed—The architecture is spe-
cifically designed to support conversion up to 210 MSPS
with outstanding dynamic performance.
2. Demultiplexed Output—Output data is decimated by two
and provided on two data ports for ease of data transport.
3. Output Data Clock—The AD9410 provides an output data
clock synchronous with the output data, simplifying the
timing between data and other logic.
4. Data Synchronization—A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or to
synchronize data to a specific output port in a single
AD9410 system.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.

No Preview Available !

AD9410* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Documentation
Application Notes
• AN-297: Test Video A/D Converters Under Dynamic
Conditions
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-835: Understanding High Speed ADC Testing and
Evaluation
Data Sheet
• AD9410: 10-Bit, 210 MSPS ADC Data Sheet
Tools and Simulations
• AD9410 IBIS Models
Reference Materials
Technical Articles
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• Designers Cast A Skeptical Eye On Mixed-Signal SOCs
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources
• AD9410 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9410 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

No Preview Available !

AD9410
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Switching Specifications .............................................................. 4
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 7
Explaination of Test Levels.......................................................... 7
ESD Caution.................................................................................. 7
REVISION HISTORY
7/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted 80-Lead LQFP_EP ...............................................Universal
Added 80-Lead TQFP_EP.................................................Universal
Changes to Figure 1 and General Description ............................. 1
Changes to Table 2 and Table 3....................................................... 4
Changes to Figure 2.......................................................................... 6
Changes to Note 1............................................................................. 7
Changes to Figure 3 and Table 6..................................................... 8
Changes to Terminology Section.................................................. 10
Changes to Figure 6........................................................................ 12
Deleted Evaluation Board Section................................................ 14
Renamed Encode Input Section, Clock Input Section and
Changes to Clock Input Section, Clock Outputs (DCO, DCO)
Section, Figure 26, and Figure 27 ................................................. 16
Changes to Data Sync (DS) Section ............................................. 17
Changes to Figure 29...................................................................... 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
Pin Configuration and Function Descriptions..............................8
Terminology .................................................................................... 10
Equivalent Circuits..................................................................... 12
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 16
Using the AD9410 ...................................................................... 16
Analog Input ............................................................................... 16
Digital Outputs ........................................................................... 16
Clock Outputs (DCO, DCO).................................................... 16
Voltage Reference ....................................................................... 17
Timing ......................................................................................... 17
Data Sync (DS) ........................................................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
10/00—Revision 0: Initial Version
Rev. A | Page 2 of 20

No Preview Available !

AD9410
SPECIFICATIONS
DC SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
No Missing Codes
Differential Nonlinearity
Integral Nonlinearity
Gain Error
Gain Temperature Coefficient
ANALOG INPUT
Input Voltage Range (With Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Reference Voltage
Reference Temperature Coefficient
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
Power Dissipation AC1
Power Dissipation DC2
IVCC2
IVD2
Power Supply Rejection Ratio, PSRR
Temp Test Level
Full IV
25°C I
Full VI
25°C I
Full VI
25°C I
Full V
Full V
Full V
25°C I
Full VI
Full VI
Full V
Full VI
25°C V
25°C V
25°C V
Full VI
Full VI
Full VI
25°C I
Min Typ
10
Guaranteed
−1.0 ±0.5
−1.0
−2.5 ±1.65
−3.0
−6.0 0
130
±768
3.0
−15 +3
−20
2.4 2.5
50
610 875
3
500
2.1
2.0
128
401
−7.5 +0.5
Max Unit
Bits
+1.25
+1.5
+2.5
+3.0
+6.0
LSB
LSB
LSB
LSB
% FS
ppm/°C
+15
+20
2.6
1250
mV p-p
V
mV
mV
V
ppm/°C
Ω
pF
MHz
W
2.4 W
145 mA
480 mA
+7.5 mV/V
1 Clock input = 210 MSPS, AIN = –0.5 dBFS, 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF.
2 Clock input = 210 MSPS, AIN = dc, outputs not switching.
Rev. A | Page 3 of 20

No Preview Available !

AD9410
SWITCHING SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 2.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock Pulse Width High, tEH
Clock Pulse Width Low, tEL
Aperture Delay, tA
Aperture Uncertainty (Jitter)
Output Valid Time, tV
Output Propagation Delay, tPD
Output Rise Time, tR
Output Fall Time, tF
CLKOUT Propagation Delay, tCPD1
Data to DCO Skew, (tPD – tCPD)
DS Setup Time, tSDS
DS Hold Time, tHDS
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
Temp
Full
Full
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Test Level
VI
IV
IV
IV
V
V
VI
VI
V
V
VI
IV
IV
IV
VI
VI
Min Typ
210
1.2 2.4
1.2 2.4
1.0
0.65
3.0
1.8
1.4
2.6 4.8
01
0.5
0
A = 6, B = 6
A = 7, B = 6
Max Unit
MSPS
100 MSPS
ns
ns
ns
ps rms
ns
7.4 ns
ns
ns
6.4 ns
2 ns
ns
ns
Cycles
Cycles
1 CLOAD = 5 pF.
DIGITAL SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
DFS, Input Logic 1 Voltage
DFS, Input Logic 0 Voltage
DFS, Input Logic 1 Current
DFS, Input Logic 0 Current
I/P Input Logic 1 Current1
I/P Input Logic 0 Current1
CLK+, CLK− Differential Input Voltage
CLK+, CLK− Differential Input Resistance
CLK+, CLK− Common-Mode Input Voltage2
DS, DS Differential Input Voltage
DS, DS Common-Mode Input Voltage
Digital Input Pin Capacitance
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3.3 V)
Logic 0 Voltage (VDD = 3.3 V)
Output Coding
Temp Test Level Min
Full IV
Full IV
Full V
Full V
Full V
Full V
Full IV
Full V
Full V
Full IV
Full V
25°C V
4
0.4
0.4
Typ Max
1
50
50
400
1
1.6
1.5
1.5
3
Full VI
Full VI
VDD – 0.05
0.05
Binary or Twos Complement
Unit
V
V
μA
μA
μA
μA
V
V
V
V
pF
V
V
1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current.
2 See Clock Input section.
Rev. A | Page 4 of 20