AD9630.pdf 데이터시트 (총 7 페이지) - 파일 다운로드 AD9630 데이타시트 다운로드

No Preview Available !

a
FEATURES
Excellent Gain Accuracy: 0.99 V/V
Wide Bandwidth: 750 MHz
Slew Rate: 1200 V/s
Low Distortion
–65 dBc @ 20 MHz
–80 dBc @ 4.3 MHz
Settling Time
5 ns to 0.1%
8 ns to 0.02%
Low Noise: 2.4 nV/Hz
Improved Source for CLC-110
APPLICATIONS
IF/Communications
Impedance Transformations
Drives Flash ADCs
Line Driving
Low Distortion 750 MHz
Closed-Loop Buffer Amp
AD9630*
PIN CONFIGURATION
+VS 1
** 2
8 OUTPUT
7 NC
NC 3
INPUT 4
6 ***
AD9630 5 –VS
NC = NO CONNECT
**OPTIONAL +VS
***OPTIONAL –VS
NOTE: FOR BEST SETTLING TIME PERFORMANCE USE
OPTIONAL POWER SUPPLIES. ALL SPECIFICATIONS
ARE BASED ON USING SINGLE ؎VS CONNECTIONS,
EXCEPT FOR SETTLING TIME TO 0.02% AND SMALL
SIGNAL S21. CONSULT THE FACTORY FOR VERSIONS
WITH OPTIONAL POWER SUPPLY PINS DISCONNECTED
INTERNAL TO THE PACKAGE.
GENERAL DESCRIPTION
The AD9630 is a monolithic buffer amplifier that utilizes a
patented, innovative, closed-loop design technique to achieve
exceptional gain accuracy, wide bandwidth, and low distortion.
Slew rate limiting has been overcome as indicated by the
1200 V/µs slew rate; this improvement allows the user greater
flexibility in wideband and pulse applications. The second har-
monic distortion terms for an analog input tone of 4.3 MHz
and 20 MHz are –80 dBc and –66 dBc, respectively. Clearly,
the AD9630 establishes a new standard by combining out-
standing dc and dynamic performance in one part.
The large signal bandwidth, low distortion over frequency, and
drive capabilities of the AD9630 make the buffer an ideal flash
ADC driver. The AD9630 provides better signal fidelity than
many of the flash ADCs that it has been designed to drive.
Other applications that require increased current drive at unity
voltage gain (such as cable driving) benefit from the AD9630’s
performance.
The AD9630 is available in plastic DIP (N) and SOIC (R).
*Protected under U.S. patent numbers 5,150,074 and 5,537,079.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1999

No Preview Available !

AD9630–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (unless otherwise noted, ؎VS = ؎5 V; RIN = 50 , RLOAD = 100 )
Parameter
DC SPECIFICATIONS
Output Offset Voltage
Offset Voltage TC
Input Bias Current
Bias Current TC
Input Resistance
Conditions
Input Capacitance
Gain
Output Voltage Range
Output Current (50 Load)
VOUT = 2 V p-p
VOUT = 2 V p-p
Output Impedance
PSRR
DC Nonlinearity
At DC
VS = ± 5%
±2 V Full Scale
FREQUENCY DOMAIN
Bandwidth (–3 dB)
Small Signal
Large Signal
Output Peaking
Output Rolloff
Group Delay
Linear Phase Deviation
2nd Harmonic Distortion
3rd Harmonic Distortion
Spectral Input Noise Voltage
Integrated Output Noise
VO 0.7 V p-p
VO 0.7 V p-p
VO = 5 V p-p
VO = 5 V p-p
200 MHz
200 MHz
DC to 150 MHz
DC to 150 MHz
2 V p-p; 4.3 MHz
2 V p-p; 20 MHz
2 V p-p; 50 MHz
2 V p-p; 4.3 MHz
2 V p-p; 20 MHz
2 V p-p; 50 MHz
2 V p-p; 50 MHz
10 MHz
100 kHz – 200 MHz
TIME DOMAIN
Slew Rate
Rise/Fall Time
Overshoot Amplitude
Settling Time
To 0.1%
To 0.02%4
Differential Gain
Differential Phase
VOUT = 5 V Step
VOUT = 1 V Step
VOUT = 1 V Step
VOUT = 5 V Step
VOUT = 5 V Step
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 2 V Step
4.4 MHz
4.4 MHz
SUPPLY CURRENTS
VCC (+IS)
VEE (–IS)
VCC = +5 V
VEE = –5 V
NOTES
1Short-term settling with 50 source impedance.
Specifications subject to change without notice.
Temp
+25°C
Full
+25°C
Full
+25 to TMAX
TMIN
+25°C
+25 to TMAX
TMIN
Full
+25 to TMAX
TMIN
+25°C
Full
+25°C
Test
Level
I
IV
I
IV
II
VI
V
II
VI
VI
II
VI
V
VI
V
AD9630AN/AR
Min Typ Max Units
–8
–40
–25
–100
300
150
0.983
0.980
+3.2
50
40
44
±3
±8
±2
± 20
450
250
1.0
0.990
0.985
± 3.6
0.6
55
0.03
+8
+40
+25
+100
–3.2
mV
µV/°C
µA
nA/°C
k
k
pF
V/V
V/V
V
mA
mA
dB
%
TMIN to +25
TMAX
TMIN to +25
TMAX
Full
Full
+25°C
+25°C
Full
Full
Full
Full
Full
TMIN to +25
TMAX
+25°C
+25°C
+25°C
+25°C
TMIN to TMAX
+25°C
TMIN to TMAX
Full
TMIN to +25
TMAX
TMIN to +25
TMAX
+25°C
+25°C
Full
Full
II
II
V
V
II
II
V
V
IV
IV
II
IV
IV
II
II
V
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
V
V
II
II
400 750
MHz
330 550
MHz
120 MHz
105 MHz
0.4 1.2 dB
0 0.3 dB
0.7 ns
0.7 Degrees
–80 –73 dBc
–66 –58 dBc
–52 –43 dBc
–86 –79 dBc
–75 –68 dBc
–47 –41 dBc
–46 –40 dBc
2.4 nV/Hz
32 µV
700 1200
V/µs
1.1 1.7 ns
1.3 1.9 ns
4.2 5.7 ns
5.0 6.5 ns
2 12 %
6
7
8
12
0.015
0.025
10
12
ns
ns
ns
ns
%
Degree
19 26 mA
19 26 mA
–2– REV. B

No Preview Available !

ABSOLUTE MAXIMUM RATINGS1
Supply Voltages (± VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 70 mA
Temperature Range over Which Specifications Apply
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300°C
Storage Temperature
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature3
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Output is short-circuit protected to ground, but not to supplies. Prolonged short
circuit to ground may affect device reliability.
3Typical thermal impedances (part soldered onto board): Plastic DIP (N): θJA =
110°C/W; θJC = 30°C/W; SOIC (R): θJA = 155°C/W; θJC = 40°C/W.
ORDERING GUIDE
Model
Temperature Package
Range
Description
Package
Option
AD9630AN
–40°C to +85°C 8-Lead Plastic DIP N-8
AD9630AR
–40°C to +85°C 8-Lead SOIC
SO-8
AD9630AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
AD9630
EXPLANATION OF TEST LEVELS
Test Level
I 100% Production tested.
II 100% Production tested at +25°C and sample tested at
specified temperatures. AC testing of AN and AR grades
done on sample basis only.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Typical value.
VI S Versions are 100% production tested at temperature
extremes. Other grades are sample tested at extremes.
+5V
0.1F
100
(5%, 0.25W)
18
NC 2 AD9630 7 NC
TOP VIEW
NC 3 (Not to Scale) 6 NC
4
24
(5%, 0.25W)
5 –5.2V
0.1F
NC = NO CONNECT
AD9630 Burn-In Circuit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
THEORY OF OPERATION
The AD9630 is a wide-bandwidth, closed-loop, unity-gain
buffer that makes use of a new voltage-feedback architecture.
This architecture brings together wide bandwidth and high slew
rate along with exceptional dc linearity. Most previous wide-
bandwidth buffers achieved their bandwidth by utilizing an
open-loop topology which sacrificed both dc linearity and fre-
quency distortion when driven into low load impedances. The
design’s high loop correction factor radically improves dc lin-
earity and distortion characteristics without diminishing
bandwidth. This, in combination with high slew rate, results in
exceptionally low distortion over a wide frequency range.
The AD9630 is an excellent choice to drive high speed and high
resolution analog-to-digital converters. Its output stage is de-
signed to drive high speed flash converters with minimal or no
series resistance. A current booster built into the output driver
helps to maintain low distortion.
Parasitic or load capacitance (>7 pF) connected directly to the
AD9630 output will result in frequency peaking. A small series
resistor (RS) connected between the buffer output and capaci-
tive load will negate this effect. Figure 1 shows the optimal value
of RS as a function of CL to obtain the flattest frequency re-
sponse. Figure 2 illustrates frequency response for various
capacitive loads utilizing the recommended RS.
50
RS
40
200
"R"
CL
30
20
NO RS NEEDED
10 WHEN CL < 7pF;
FOR CL > 30pF, "R"
CAN BE OMITTED
0
07
20
40 60
CL – pF
80
Figure 1. Recommended RS vs. CL
100
REV. B
–3–

No Preview Available !

AD9630
2
1
10pF
0
25pF
–1
50pF
–2
–3
–4
–5
–6
–7
–8
<0.1MHz
100MHz
200MHz
CL
300MHz
Figure 2. Frequency Response vs. CL
with Recommended RS
In pulse mode applications, with RS equal to approximately
12 , capacitive loads of up to 50 pF can be driven with mini-
mal settling time degradation.
The output stage has short circuit protection to ground. The
output driver will shut down if more than approximately
130 mA of instantaneous sink or source current is reached. This
level of current ensures that output clipping will not result when
driving heavy capacitive loads during high slew conditions,
although average load currents above 70 mA may reduce device
reliability.
LAYOUT CONSIDERATIONS
Due to the high frequency operation of the AD9630 attention to
board layout is necessary to achieve optimum dynamic perfor-
mance. A two ounce copper ground plane on the top side of the
board is recommended; it should cover as much of the board as
possible with appropriate openings for supply decoupling ca-
pacitors as well as for load and source termination resistors, (see
Figure 3).
Optimum settling time and ac performance results will be
achieved with surface mount 0.1 µF supply decoupling ceramic
chip capacitors mounted within 50 mils of the corresponding
device pins with the other side soldered directly to the ground
plane. For best high resolution (<0.02%) settling times, the op-
tional power supply pins should be decoupled as shown above.
If the optional power supply pins are not used, they should be
left open.
If surface mount capacitors cannot be used, radial lead ceramic
capacitors with leads less than 30 mils long are recommended.
Low frequency power supply decoupling is necessary and can be
accomplished with 4.7 µF tantalum capacitors mounted within
0.5 inches of the supply pins. Due to the series inductance of
these capacitors interacting with the 0.1 µF capacitors and
power supply leads, high frequency oscillations might appear on
the device output. To avoid this occurrence, the power supply
leads should be tightly twisted (if appropriate). Ferrite beads
mounted between the tantalum and ceramic capacitors will
serve the same purpose.
All unused pins (except the optional power supply pins) should
be connected to ground to reduce pin-to-pin capacitive coupling
and prevent external RF interference. If the source and drive
electronics require “remote” operation (> 1 inch from the
AD9630), the PC board line impedances should be matched
with the buffer input and output resistances. Basic microstrip
techniques should be observed. RIN and RS should be connected
as close to the AD9630 as possible.
With only minimal pulse overshoot and ringing, the AD9630
can drive terminated cables directly without the use of an output
termination resistor (RS). Termination resistors (RS and RIN)
can be either standard carbon composition or microwave type.
For matching characteristic impedances, precision microwave
resistors of 1% or better tolerance are preferred.
The AD9630 should be soldered directly to the PC board with
as little vertical clearance as possible. The use of zero insertion
sockets is strongly discouraged because of the high effective pin
inductances. Use of this type socket will result in peaking and
possibly induce oscillation.
+VS 4.7F
0.1F
0.1F
VIN
RIN
1
2*
AD9630 8
6*
5
0.1F
RS**
VOUT
0.1F
4.7F
–VS
*SEE PINOUTS
**SEE FIGURE 1
Figure 3. AD9630 Application Circuit
–4– REV. B

No Preview Available !

0
–100
–200
RL = 200
–300
–400
–500
RL = 100
–600
–700
–800
–900
–1000
–3
–2 –1 0 1
VOLTS
23
Figure 4. Endpoint DC Linearity
50
40
30
20
10
0
1M
10M
100M
1G
FREQUENCY – Hz
Figure 7. PSRR vs. Frequency
Typical Performance Curves – AD9630
1M
100k
10k
1k
100
10
1
1M
10M
100M
FREQUENCY – Hz
1G
Figure 5. Input Impedance
30 100
25 80
20 60
|Zo|
15 40
10 20
50
0
1M
10M
100M
1G
FREQUENCY – Hz
Figure 6. Output Impedance
50
50
40
50
TEST
CIRCUIT
30
20
10
0
dc 50 100 150 200 250
FREQUENCY – MHz
Figure 8. 2-Tone Intermodulation
Distortion
10 50
8 40
6 30
4 20
BIAS CURRENT
2 10
00
–2 –10
–4 –20
–6
OFFSET VOLTAGE
–30
–8
–10
–55
25
CASE TEMPERATURE – ؇C
–40
–50
125
Figure 9. Offset Voltage and Bias
Current vs. Temperature
2
VIN = 100mV
1
0
–1 VIN = 750mV
–2
–3 PHASE
–4
VIN = 100mV
–5
–6
GAIN
0
–45
–90
–135
–180
–7
–8
0M
200M 400M 600M 800M
FREQUENCY – Hz
1G
Figure 10 . Forward Gain and Phase
3
2
1 RL = 200
0
–1 RL = 50RL = 100
–2
–3
–4
–5
–6
–7
0
40 80 120 160
FREQUENCY – MHz
200
Figure 11. Frequency Response vs.
RLOAD
0.5
0.25
0
–0.25
–0.5
TEST CIRCUIT
50
50
6pF
2ns/DIVISION
Figure 12. Small-Signal Pulse
Response
REV. B
–5–