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FEATURES
8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual port or interleaved data
On-chip 1.2 V reference
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
GENERAL DESCRIPTION
The AD97091 is a dual-port, high speed, 2-channel, 8-bit CMOS
DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage
reference, and digital interface circuitry into a small 48-lead LQFP
package. The AD9709 offers exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports independent
of one another. Separate clocks control the update rate of the DACs.
A mode control pin allows the AD9709 to interface to two separate
data ports, or to a single interleaved high speed data port. In inter-
leaving mode, the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then converted
by the two DACs and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the Gain
Control Mode section for important date code information on
this feature.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
1 Patent pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
8-Bit, 125 MSPS, Dual TxDAC+
Digital-to-Analog Converter
AD9709
FUNCTIONAL BLOCK DIAGRAM
DVDD1/ DCOM1/
DVDD2 DCOM2 AVDD ACOM CLK1
PORT1
WRT1/IQWRT
WRT2/IQSEL
PORT2
1
LATCH
1
DAC
DIGITAL
INTERFACE
AD9709
REFERENCE
BIAS
GENERATOR
2
LATCH
2
DAC
MODE
CLK2/IQ RESET
Figure 1.
IOUTA1
IOUTB1
REFIO
FSADJ1
FSADJ2
GAINCTRL
SLEEP
IOUTA2
IOUTB2
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output, thus supporting single-
ended or differential applications. Both DACs can be
simultaneously updated and provide a nominal full-scale
current of 20 mA. The full-scale currents between each DAC
are matched to within 0.1%.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.3 V or 5 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9709 is a member of a pin-compatible family of
dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance
DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.
3. Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
4. Low Power. Complete CMOS dual DAC function operates
at 380 mW from a 3.3 V or 5 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V
temperature-compensated band gap voltage reference.
6. Dual 8-Bit Inputs. The AD9709 features a flexible dual-
port interface, allowing dual or interleaved input data.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.

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AD9709* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD9709 Evaluation Board
Documentation
Application Notes
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-320A: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifier, Part 1
• AN-555: Using the AD9709, AD9763, AD9765, AD9767
Dual DAC Evaluation Board
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
• AD9709: 8-Bit, 125 MSPS Dual TxDAC+® D/A Converter
Data Sheet
Tools and Simulations
• AD9709 IBIS Models
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD9709 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9709 EngineerZone Discussions
Sample and Buy
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Technical Support
Submit a technical question or find your regional support
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the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
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AD9709
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
DC Specifications ......................................................................... 3 
Dynamic Specifications ............................................................... 4 
Digital Specifications ................................................................... 5 
Absolute Maximum Ratings............................................................ 6 
Thermal Resistance ...................................................................... 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 8 
Terminology .................................................................................... 11 
Theory of Operation ...................................................................... 12 
Functional Description.............................................................. 12 
Reference Operation .................................................................. 13 
Gain Control Mode .................................................................... 13 
Setting the Full-Scale Current................................................... 13 
DAC Transfer Function ............................................................. 14 
REVISION HISTORY
9/09—Rev. A to Rev. B
Changes to Power and Grounding Considerations Section ..... 20
Changes to Schematics Section..................................................... 24
Changes to Evaluation Board Layout Section............................. 30
1/08—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changed Single Supply Operation to 5 V or 3.3 V ........Universal
Changes to Figure 1.......................................................................... 1
Added Timing Diagram Section .................................................... 5
Changes to Figure 3 and Table 6..................................................... 7
Change to Figure 12 ......................................................................... 9
Changes to Figure 18 to Figure 20................................................ 10
Changes to Functional Description Section ............................... 13
Changes to Reference Operation Section.................................... 13
Changes to Figure 23 and Figure 24............................................. 13
Changes to Gain Control Mode Section...................................... 13
Analog Outputs .......................................................................... 14 
Digital Inputs .............................................................................. 15 
DAC Timing................................................................................ 15 
Sleep Mode Operation............................................................... 18 
Power Dissipation....................................................................... 18 
Applying the AD9709 .................................................................... 19 
Output Configurations .............................................................. 19 
Differential Coupling Using a Transformer............................ 19 
Differential Coupling Using an Op Amp................................ 19 
Single-Ended, Unbuffered Voltage Output............................. 20 
Single-Ended, Buffered Voltage Output Configuration........ 20 
Power and Grounding Considerations.................................... 20 
Applications Information .............................................................. 22 
Quadrature Amplitude Modulation (QAM) Using the
AD9709........................................................................................ 22 
CDMA ......................................................................................... 23 
Evaluation Board ............................................................................ 24 
General Description................................................................... 24 
Schematics................................................................................... 24 
Evaluation Board Layout........................................................... 30 
Outline Dimensions ....................................................................... 32 
Ordering Guide .......................................................................... 32 
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section...................................................... 13
Changes to DAC Transfer Function Section............................... 14
Changes to Interleaved Mode Timing Section ........................... 16
Added Figure 28 ............................................................................. 16
Changes to Power and Grounding Considerations Section ..... 20
Changes to Figure 44...................................................................... 22
Deleted Figure 43............................................................................ 17
Changes to CDMA Section ........................................................... 23
Changes to Figure 45 Caption ...................................................... 23
Changes to Figure 46...................................................................... 24
Changes to Figure 48...................................................................... 26
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
5/00—Revision 0: Initial Version
Rev. B | Page 2 of 32

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AD9709
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
Min Typ Max
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
8
−0.5 ±0.1 +0.5
Differential Nonlinearity (DNL)
−0.5 ±0.1 +0.5
ANALOG OUTPUT
Offset Error
−0.02
+0.02
Gain Error Without Internal Reference
Gain Error with Internal Reference
Gain Match
TA = 25°C
TMIN to TMAX
TMIN to TMAX
Full-Scale Output Current2
−2
−5
−0.3
−1.6
−0.14
2.0
±0.25
+1
±0.1
+2
+5
+0.3
+1.6
+0.14
20.0
Output Compliance Range
−1.0 +1.25
Output Resistance
Output Capacitance
100
5
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14 1.20 1.26
100
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small-Signal Bandwidth
0.1 1.25
1
0.5
TEMPERATURE COEFFICIENTS
Offset Drift
0
Gain Drift Without Internal Reference
±50
Gain Drift with Internal Reference
±100
Reference Voltage Drift
±50
POWER SUPPLY
Supply Voltages
AVDD
DVDD1, DVDD2
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Digital Supply Current (IDVDD)5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio7—AVDD
Power Supply Rejection Ratio7—DVDD1, DVDD2
3 5 5.5
2.7 5 5.5
71 75
57
15
8 12
380 410
420 450
450
−0.4 +0.4
−0.025
+0.025
OPERATING RANGE
−40 +85
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
dB
mA
V
pF
V
nA
V
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
mA
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz.
5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz.
6 Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz.
7 ±10% power supply variation.
Rev. B | Page 3 of 32

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AD9709
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω
doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLK)
Output Settling Time (tST) to 0.1%1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLK = 100 MSPS, fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLK = 65 MSPS, fOUT = 1.00 MHz
fCLK = 65 MSPS, fOUT = 2.51 MHz
fCLK = 65 MSPS, fOUT = 5.02 MHz
fCLK = 65 MSPS, fOUT = 14.02 MHz
fCLK = 65 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Signal to Noise and Distortion Ratio
fCLK = 50 MHz, fOUT = 1 MHz
Total Harmonic Distortion
fCLK = 100 MSPS, fOUT = 1.00 MHz
fCLK = 50 MSPS, fOUT = 2.00 MHz
fCLK = 125 MSPS, fOUT = 4.00 MHz
fCLK = 125 MSPS, fOUT = 10.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
Channel Isolation
fCLK = 125 MSPS, fOUT = 10 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Min Typ Max Unit
125
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
63 68
62
56
50
68
68
66
60
50
63
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
50 dB
−67 −63
−63
−63
−63
dBc
dBc
dBc
dBc
58 dBc
51 dBc
46 dBc
41 dBc
85 dBc
77 dBc
1 Measured single-ended into 50 Ω load.
Rev. B | Page 4 of 32