AD9732.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 AD9732 데이타시트 다운로드

No Preview Available !

a
10-Bit, 200 MSPS
D/A Converter
AD9732
FEATURES
200 MSPS Throughput Rate
3.3 V PECL Digital Input
65 dB SFDR @ 2 MHz AOUT, 200 MSPS/54 dB @ 40 MHz
AOUT, 200 MSPS
Low Power: 305 mW
Fast Settling: 5 ns to 1/2 LSB
Low Glitch Energy: 6 pVs
Internal Reference
28-Lead SSOP Packaging
APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
CLOCK
FUNCTIONAL BLOCK DIAGRAM
ANALOG
RETURN
TTL
DRIVE
LOGIC
IOUT
IOUT
INTERNAL
VOLTAGE
REFERENCE
REFIN
CONTROL
AMP
AD9732
CONTROL
AMP OUT
GENERAL DESCRIPTION
The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that
is optimized to provide high dynamic performance, yet offers
lower power dissipation and a more economical price than pre-
vious high speed DAC solutions. The AD9732 was primarily
designed for demanding communications systems applications
where maximum spurious-free dynamic range (SFDR) is required
at high throughput rates. The proliferation of digital communi-
cations into base station and high volume subscriber-end mar-
kets has created a demand for high performance bipolar DACs
delivered at CMOS associated levels of power dissipation and
cost. The AD9732 is the answer to that demand.
Optimized for direct digital synthesis (DDS) and digital modu-
lator waveform reconstruction, the AD9732 provides >50 dB of
wideband harmonic suppression over the dc to 80 MHz analog
output bandwidth. This signal bandwidth addresses the transmit
RSET
REFOUT
CONTROL
AMP IN
DIGITAL
+VS
spectrum in many of the emerging digital communications ap-
plications where signal purity is critical. Narrowband (± 1 MHz
window), the AD9732 provides an SFDR of greater than 75 dB.
This level of wideband and narrowband ac performance, coupled
with its 200 MSPS throughput rate, enables the AD9732 to
present outstanding value in the high speed DAC function.
The AD9732 is packaged in a 28-lead SSOP and is specified to
operate over the extended industrial temperature range of –40°C
to +85°C. Digital inputs and clock are positive-ECL compatible.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

No Preview Available !

AD9732–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+VS = +5 V, ENCODE = 125 MSPS, RSET = 1.95 k(for 20 mA IOUT) unless otherwise noted)
Parameter
Temp
Test
Level
AD9732BRS
Min Typ Max
Units
THROUGHPUT RATE
+25°C
IV
165 200
MHz
RESOLUTION
10 Bits
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
VI
0.25 1
0.36 1
0.6 1.5
0.7 1.5
LSB
LSB
LSB
LSB
INITIAL OFFSET ERROR
Zero-Scale Offset Error
Full-Scale Gain Error1
Offset Drift Coefficient
+25°C
Full
+25°C
Full
I
VI
I
VI
V
35 70
40 100
2.5 5
2.5 5
0.04
µA
µA
% FS
% FS
µA/°C
REFERENCE/CONTROL AMP
Internal Reference Voltage2
Internal Reference Voltage Drift
Internal Reference Output Current3
Amplifier Input Impedance
Amplifier Bandwidth
REFERENCE INPUT4
Reference Input Impedance
Reference Multiplying Bandwidth5
+25°C
Full
Full
+25°C
+25°C
+25°C
+25°C
I
IV
VI
I
I
V
V
3.65 3.75 3.85
150
–50 +500
50
2.5
4.6
75
V
µV/°C
µA
k
MHz
k
MHz
OUTPUT PERFORMANCE
Output Current4, 6
Full V 20 mA
Output Compliance
Full IV 2
5.75 V
Output Resistance
+25°C
V
240
Output Capacitance
+25°C
V
5
pF
Voltage Settling Time to 1/2 LSB (tST)7
Propagation Delay (tPD)8
Glitch Impulse9
+25°C
+25°C
Full
V
V
V
4.75 ns
2.7 ns
5.9 pVs
Output Slew Rate10
Output Rise Time10
Full V
Full V
450 V/µs
1 ns
Output Fall Time10
Full V
1
ns
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Minimum Data Setup Time (tS)11
Minimum Data Hold Time (tH)12
Clock Pulsewidth Low (pwMIN)
Clock Pulsewidth High (pwMAX)
POWER SUPPLY13
Digital +V Supply Current
Analog +V Supply Current
Power Dissipation14
Power Supply Rejection Ratio (PSRR)
Full
Full
+25°C
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
VI
VI
I
I
V
IV
IV
IV
IV
IV
IV
I
VI
I
VI
V
V
V
2.4
1.6
1.7 10
–1 0.01 1
2
0.7 1.5
1 1.5
0.7 1.5
1 1.5
2
2
15 25 35
10 40
10 20 30
10 30
305
350
200
V
V
µA
µA
pF
ns
ns
ns
ns
ns
ns
mA
mA
mA
mA
mW
mW
µA/V
–2– REV. A

No Preview Available !

AD9732
Parameter
Temp
Test
Level
AD9732BRS
Min Typ Max
Units
SFDR PERFORMANCE (Wideband)15
2 MHz AOUT
+25°C
V
66
dB
10 MHz AOUT
+25°C
V
63
dB
20 MHz AOUT
+25°C
V
57
dB
40 MHz AOUT
+25°C
V
52
dB
2 MHz AOUT (Clock = 165 MHz)
+25°C
V
63
dB
10 MHz AOUT (Clock = 165 MHz)
+25°C
V
62
dB
20 MHz AOUT (Clock = 165 MHz)
+25°C
V
56
dB
40 MHz AOUT (Clock = 165 MHz)
+25°C
V
51
dB
65 MHz AOUT (Clock = 165 MHz)
+25°C
V
48
dB
65 MHz AOUT (Clock = 200 MHz)
+25°C
V
45
dB
80 MHz AOUT (Clock = 200 MHz)
+25°C
V
43
dB
SFDR PERFORMANCE (Narrowband)15
2 MHz; 2 MHz Span
+25°C
V
77
dB
25 MHz; 2 MHz Span
+25°C
V
65
dB
10 MHz; 5 MHz Span (Clock = 200 MHz)
+25°C
V
70
dB
INTERMODULATION DISTORTION16
F1 = 800 kHz, F2 = 900 kHz to Nyquist
+25°C
V
69
dB
F1 = 800 kHz, F2 = 900 kHz, Narrowband
(2 MHz)
+25°C
V
61
dB
NOTES
1Measured as an error in ratio of full-scale current to current through R SET (640 µA nominal); ratio is nominally 32. DAC load is virtual ground.
2Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification.
3Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5Frequency at which a 3 dB change in output of DAC is observed; R L = 50 ; 100 mV modulation at midscale.
6Based on IFS = 32 ([CONTROL AMP IN – (+VS)]/RSET) when using internal control amplifier. DAC load is virtual ground.
7Measured as voltage settling at midscale transition to 0.1%; RL = 50 .
8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10Measured with RL = 50 and DAC operating in latched mode.
11Data must remain stable for a specified time prior to rising edge of CLOCK.
12Data must remain stable for a specified time after rising edge of CLOCK.
13Supply voltages should remain stable with ±5% for nominal operation.
14Power dissipation calculation includes current through a 50 load.
15SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span dc to Nyquist unless otherwise noted.
16Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I 100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range.
Model
AD9732BRS
AD9732/PCB
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
+25°C
Package
Description
28-Lead Small Outline (SSOP)
Evaluation Board
Package
Option
RS-28
REV. A
–3–

No Preview Available !

AD9732
ABSOLUTE MAXIMUM RATINGS*
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+VS
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to +VS
Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA
Control Amplifier Output Current . . . . . . . . . . . . . . ± 2.5 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Lead Temperature (10 sec) Soldering . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
PIN CONFIGURATION
D9 (MSB) 1
D8 2
28 DIGITAL +VS
27 GND
D7 3
26 CONTROL AMP IN
D6 4
25 REF OUT
D5 5
24 CONTROL AMP OUT
D4 6
23 REF IN
AD9732
D3 7 TOP VIEW 22 GND
D2 8 (Not to Scale) 21 IOUTB
D1 9
20 IOUT
D0 (LSB) 10
19 ANALOG RETURN
CLOCK 11
NC 12
NC 13
18 ANALOG +VS
17 RSET
16 GND
DIGITAL +VS 14
15 DIGITAL +VS
NC = NO CONNECT
Pin Number
1
2–9
10
11
12, 13
14, 15, 28
16, 22, 27
18
17
19
20
21
23
24
25
26
Name
D9 (MSB)
D8–D1
D0 (LSB)
CLOCK
NC
DIGITAL +VS
GND
ANALOG +VS
RSET
ANALOG RETURN
IOUT
IOUTB
REF IN
CONTROL AMP OUT
REF OUT
CONTROL AMP IN
PIN FUNCTION DESCRIPTIONS
Function
Most significant data bit of digital input word.
Eight bits of 10-bit digital input word.
Least significant data bit of digital input word.
TTL-compatible edge-triggered latch enable signal for on-board registers.
No internal connection to this pin. Recommend tie to ground.
+5 V supply voltage for digital circuitry.
Converter Ground.
+5 V supply voltage for analog circuitry.
Connection for external reference set resistor; nominal 1.96 k. Full-scale output
current = 32 [Control Amp + VS] (Reset).
Analog Return. This point and the reference side of the DAC load resistors should be
connected to the same potential (Analog +VS).
Analog current output; full-scale current occurs with a digital word input of all “1s”
with external load resistor, output voltage = IOUT (RLOADʈRINTERNAL). RINTERNAL is
nominally 240 .
Complementary analog current output; full-scale current occurs with a digital word
input of all “0s.”
Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current
source network. Voltage changes (noise) at this point have a direct effect on the full-
scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/
RSET) when using internal amplifier. DAC load is virtual ground.
Normally connected to REF IN (Pin 23). Output of internal control amplifier, which
provides a reference for the current switch network.
Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference,
nominally 3.75 V.
Normally connected to REF OUT (Pin 25) if not connected to external reference.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9732 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. A

No Preview Available !

AD9732
CLOCK
DATA
tS
CODE 1
DATA
pwMIN
pwMAX
tH
CODE 2
DATA
CODE 3
DATA
CODE 4
DATA
ANALOG OUTPUT
CODE 1
CODE 2
CODE 3
CODE 4
DETAIL OF SETTLING TIME
CLOCK
tPD
SPECIFIED
ERROR BAND
ANALOG OUTPUT
tST
b.
a.
GLITCH AREA = 1/2 HEIGHT ؋ WIDTH
H
W
c.
Figure 1. Timing Diagrams
REV. A
–5–