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a
12-Bit, 125 MSPS High Performance
TxDAC® D/A Converter
AD9752*
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 79 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9752 is a 12-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC family,
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package and pinout, thus providing an upward or
downward component selection path based on performance,
resolution and cost. The AD9752 offers exceptional ac and dc
performance while supporting update rates up to 125 MSPS.
The AD9752’s flexible single-supply operating range of 4.5 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 20 mW.
The AD9752 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V to +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
5703519. Other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
RSET +5V
CLOCK
REFLO
+1.20V REF
REFIO
FS ADJ
150pF
AVDD ACOM
CURRENT
SOURCE
ARRAY
AD9752
ICOMP 0.1F
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
SLEEP
LATCHES
DIGITAL DATA INPUTS (DB11–DB0)
The AD9752 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 koutput impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9752 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9752 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9752 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9752 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9752 is a member of the wideband TxDAC product
family that provides an upward or downward component selec-
tion path based on resolution (8 to 14 bits), performance and
cost. The entire family of TxDACs is available in industry
standard pinouts.
2. Manufactured on a CMOS process, the AD9752 uses a
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +2.7 V to +5 V CMOS logic families. The AD9752 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 4.5 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9752 to operate at reduced power levels.
5. The current output(s) of the AD9752 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

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AD9752–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min Typ Max
RESOLUTION
12
DC ACCURACY1
Integral Linearity Error (INL)
TA = +25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = +25°C
TMIN to TMAX
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–1.5
–2.0
–0.75
–1.0
–0.02
–2
–5
2.0
–1.0
± 0.5
± 0.25
± 0.5
± 1.5
100
5
+1.5
+2.0
+0.75
+1.0
+0.02
+2
+5
20.0
1.25
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14 1.20 1.26
100
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
0.1 1.25
1
0.5
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0
± 50
± 100
± 50
POWER SUPPLY
Supply Voltages
AVDD
DVDD
Analog Supply Current (IAVDD)4
Digital Supply Current (IDVDD)5
Supply Current Sleep Mode (IAVDD)6
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio7—AVDD
Power Supply Rejection Ratio7—DVDD
4.5
2.7
–0.4
–0.025
5.0
5.0
34
3
4
185
5.5
5.5
39
5
8
220
+0.4
+0.025
OPERATING RANGE
–40
+85
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3Use an external buffer amplifier to drive any external load.
4Requires +5 V supply.
5Measured at fCLOCK = 25 MSPS and IOUT = static full scale (20 mA).
6Logic level for SLEEP pin must be referenced to AVDD. Min VIH = 3.5 V.
7± 5% Power supply variation.
Specifications subject to change without notice.
Units
Bits
LSB
LSB
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
k
pF
V
nA
V
M
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
mA
mA
mA
mW
% of FSR/V
% of FSR/V
°C
–2– REV. 0

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AD9752
DYNAMIC SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
0 dBFS Output
TA = +25°C
–6 dBFS Output
–12 dBFS Output
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 2.51 MHz
fCLOCK = 50 MSPS; fOUT = 5.02 MHz
fCLOCK = 50 MSPS; fOUT = 14.02 MHz
fCLOCK = 50 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 2.5 MHz
fCLOCK = 100 MSPS; fOUT = 5 MHz
fCLOCK = 100 MSPS; fOUT = 20 MHz
fCLOCK = 100 MSPS; fOUT = 40 MHz
Spurious-Free Dynamic Range within a Window
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
TA = +25°C
fCLOCK = 50 MHz; fOUT = 2.00 MHz
fCLOCK = 100 MHz; fOUT = 2.00 MHz
Multitone Power Ratio (8 Tones at 110 kHz Spacing)
fCLOCK = 20 MSPS; fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
NOTES
1Measured single ended into 50 load.
Specifications subject to change without notice.
Min Typ Max
125
35
1
5
2.5
2.5
50
30
Units
MSPS
ns
ns
pV-s
ns
ns
pA/Hz
pA/Hz
75 84
76
81
81
81
76
62
60
78
76
63
55
84 93
86
86
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
–82 –74
–76
–76
dBc
dBc
dBc
81 dBc
81 dBc
85 dBc
86 dBc
REV. 0
–3–

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AD9752
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min Typ Max
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V1
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V1
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
3.5 5
2.1 3
0 1.3
0 0.9
–10 +10
–10 +10
5
2.0
1.5
3.5
NOTES
1When DVDD = +5 V and Logic 1 voltage 3.5 V and Logic 0 voltage 1.3 V. IVDD can increase by up to 10 mA, depending on fCLOCK.
Specifications subject to change without notice.
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
tS tH
tLPW
tPD tST
0.1%
0.1%
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect to Min Max
Units
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
ICOMP
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
–0.3 +6.5
V
–0.3 +6.5
V
–0.3 +0.3
V
–6.5 +6.5
V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–1.0 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 +0.3
V
+150
°C
–65 +150
°C
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Model
Temperature Package
Range
Description
Package
Options*
AD9752AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9752ARU –40°C to +85°C 28-Lead TSSOP
RU-28
AD9752-EB
Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
θJA = 71.4°C/W
θJC = 23°C/W
28-Lead TSSOP
θJA = 97.9°C/W
θJC = 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9752 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. 0

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PIN CONFIGURATION
(MSB) DB11 1
28 CLOCK
DB10 2
27 DVDD
DB9 3
26 DCOM
DB8 4
25 NC
DB7 5 AD9752 24 AVDD
DB6 6 TOP VIEW 23 ICOMP
DB5 7 (Not to Scale) 22 IOUTA
DB4 8
21 IOUTB
DB3 9
20 ACOM
DB2 10
19 NC
DB1 11
18 FS ADJ
DB0 12
17 REFIO
NC 13
16 REFLO
NC 14
15 SLEEP
NC = NO CONNECT
AD9752
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2–11
12
13, 14,
19, 25
15
16
17
18
19
20
21
22
23
24
26
27
28
Name
Description
DB11
Most Significant Data Bit (MSB).
DB10–DB1 Data Bits 1–10.
DB0 Least Significant Data Bit (LSB).
NC
SLEEP
REFLO
REFIO
FS ADJ
NC
ACOM
IOUTB
IOUTA
ICOMP
AVDD
DCOM
DVDD
CLOCK
No Internal Connection.
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated
if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
No Connect.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
Analog Supply Voltage (+4.5 V to +5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
REV. 0
–5–