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FEATURES
12-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 69 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155 mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM
12-Bit, 300 MSPS
High Speed TxDAC+®D/A Converter
AD9753*
FUNCTIONAL BLOCK DIAGRAM
DVDD DCOM
AVDD ACOM
PORT1
LATCH
PORT2
LATCH
MUX
DAC
IOUTA
IOUTB
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
PLL
CLOCK
MULTIPLIER
REFERENCE
AD9753
RESET LPF DIV0 DIV1 PLLLOCK
REFIO
FSADJ
GENERAL DESCRIPTION
The AD9753 is a dual, muxed port, ultrahigh speed, single-
channel, 12-bit CMOS DAC. It integrates a high quality 12-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9753 offers excep-
tional ac and dc performance while supporting update rates up
to 300 MSPS.
The AD9753 has been optimized for ultrahigh speed applica-
tions up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differen-
tially or single-ended, with a signal swing as low as 1 V p-p.
The DAC utilizes a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and to maximize dynamic accuracy. Differential
current outputs support single-ended or differential applica-
tions. The differential outputs each provide a nominal full-scale
current from 2 mA to 20 mA.
The AD9753 is manufactured on an advanced low cost 0.35 µm
CMOS process. It operates from a single supply of 3.0 V to 3.6 V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9753 is a member of a pin compatible family of high
speed TxDAC+s providing 10-, 12-, and 14-bit resolution.
2. Ultrahigh Speed 300 MSPS Conversion Rate.
3. Dual 12-Bit Latched, Multiplexed Input Ports. The AD9753
features a flexible digital interface allowing high speed data
conversion through either a single or dual port input.
4. Low Power. Complete CMOS DAC function operates on
155 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation.
5. On-Chip Voltage Reference. The AD9753 includes a 1.20 V
temperature-compensated band gap voltage reference.
*Protected by U.S. Patent numbers 5450084, 5568145, 5689257, and
5703519.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

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AD9753* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD9753 Evaluation Board
Documentation
Application Notes
• AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-320A: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifier, Part 1
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
• AN-642: Coupling a Single-Ended Clock Source to the
Differential Clock Input of Third-Generation TxDAC® and
TxDAC+® Products
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
• AD9753: 12-Bit, 300 MSPS High-Speed TxDAC+® D/A
Converter Data Sheet
Tools and Simulations
• AD9753 IBIS Models
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD9753 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9753 EngineerZone Discussions
Sample and Buy
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Technical Support
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number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

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AD9753–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless
otherwise noted.)
Parameter
Min
Typ
Max
Unit
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
12 Bits
–1.5 ± 0.5 +1.5 LSB
–1
± 0.4 +1
LSB
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–0.025
–2
–2
2.0
–1.0
± 0.01
± 0.5
± 0.25
100
5
+0.025
+2
+2
20.0
+1.25
% of FSR
% of FSR
% of FSR
mA
V
k
pF
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14 1.20 1.26 V
100 nA
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
0.1
1
1.25 V
M
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0
± 50
± 100
± 50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
POWER SUPPLY
Supply Voltages
AVDD
DVDD
PLLVDD
CLKVDD
Analog Supply Current (IAVDD)4
Digital Supply Current (IDVDD)4
PLL Supply Current (IPLLVDD)4
Clock Supply Current (ICLKVDD)4
Power Dissipation4 (3 V, IOUTFS = 20 mA)
Power Dissipation5 (3 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio6—AVDD
Power Supply Rejection Ratio6—DVDD
OPERATING RANGE
3.0
3.0
3.0
3.0
–1
–0.04
–40
3.3
3.3
3.3
3.3
33
3.5
4.5
10.0
155
216
3.6
3.6
3.6
3.6
36
4.5
5.1
11.5
165
+1
+0.04
+85
V
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32× the IREF current.
3An external buffer amplifier is recommended to drive any external load.
4100 MSPS fDAC with PLL on, fOUT = 1 MHz, all supplies = 3.0 V.
5300 MSPS fDAC.
6± 5% power supply variation.
Specifications subject to change without notice.
–2– REV.B

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AD9753
DYNAMIC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3.3 V, IOUTFS = 20 mA,
Differential Transformer-Coupled Output, 50 V Doubly Terminated, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fDAC)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)1
Glitch Impulse1
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
300
11
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/Hz
pA/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fDAC = 100 MSPS; fOUT = 1.00 MHz
0 dBFS Output
72 82
dBc
–6 dBFS Output
76 dBc
–12 dBFS Output
76 dBc
fDATA = 65 MSPS; fOUT = 1.1 MHz2
fDATA = 65 MSPS; fOUT = 5.1 MHz2
fDATA = 65 MSPS; fOUT = 10.1 MHz2
fDATA = 65 MSPS; fOUT = 20.1 MHz2
fDATA = 65 MSPS; fOUT = 30.1 MHz2
fDAC = 200 MSPS; fOUT = 1.1 MHz
fDAC = 200 MSPS; fOUT = 11.1 MHz
fDAC = 200 MSPS; fOUT = 31.1 MHz
fDAC = 200 MSPS; fOUT = 51.1 MHz
fDAC = 200 MSPS; fOUT = 71.1 MHz
fDAC = 300 MSPS; fOUT = 1.1 MHz
fDAC = 300 MSPS; fOUT = 26.1 MHz
fDAC = 300 MSPS; fOUT = 51.1 MHz
fDAC = 300 MSPS; fOUT = 101.1 MHz
fDAC = 300 MSPS; fOUT = 141.1 MHz
Spurious-Free Dynamic Range within a Window
77 dBc
77 dBc
76 dBc
72 dBc
68 dBc
78 dBc
75 dBc
70 dBc
70 dBc
67 dBc
78 dBc
69 dBc
65 dBc
59 dBc
58 dBc
fDAC = 100 MSPS; fOUT = 1 MHz; 2 MHz Span
0 dBFS Output
82.5 92
dBc
fDAC = 65 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fDAC = 150 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
85 dBc
85 dBc
fDAC = 100 MSPS; fOUT = 1.00 MHz
0 dBFS
–82 –71 dBc
fDAC = 65 MHz; fOUT = 2.00 MHz
fDAC = 160 MHz; fOUT = 2.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
–76
–76
dBc
dBc
fDAC = 65 MSPS; fOUT = 2.00 MHz to 2.77 MHz
0 dBFS Output
73 dBc
–6 dBFS Output
71 dBc
–12 dBFS Output
69 dBc
NOTES
1Measured single-ended into 50 load.
2Single-Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1).
Specifications subject to change without notice.
REV. B
–3–

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AD9753
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1
2.1 3
V
Logic 0
0 0.9 V
Logic 1 Current
–10 +10 µA
Logic 0 Current
–10 +10 µA
Input Capacitance
5 pF
Input Setup Time (tS), TA = 25°C
1.0 0.5
Input Hold Time (tH), TA = 25°C
1.0 0.5
Latch Pulsewidth (tLPW), TA = 25°C
1.5
Input Setup Time (tS, PLLVDD = 0 V), TA = 25°C
–1.0 –1.5
Input Hold Time (tH, PLLVDD = 0 V), TA = 25°C
2.5 1.7
CLK to PLLLOCK Delay (tD, PLLVDD = 0 V), TA = 25°C
3.5
4.0
Latch Pulsewidth (tLPW PLLVDD = 0 V), TA = 25°C
1.5
PLLOCK (VOH)
3.0
PLLOCK (VOL)
0.3
ns
ns
ns
ns
ns
ns
ns
V
V
CLK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
Min CLK Frequency*
0 3V
0.75 1.5
2.25 V
0.5 1.5
V
6.25 MHz
*Min CLK Frequency applies only when using internal PLL. When PLL is disabled, there is no minimum CLK frequency.
Specifications subject to change without notice.
–4– REV. B