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10-Bit, 125 MSPS
TxDAC® D/A Converter
AD9760
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
Set Top Boxes
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans-
mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
0.1F
RSET +5V
CLOCK
REFLO
+1.20V REF
REFIO
FS ADJ
COMP1 AVDD ACOM
50pF
AD9760
CURRENT
SOURCE
ARRAY
0.1F
COMP2
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
SLEEP
LATCHES
DIGITAL DATA INPUTS (DB9–DB0)
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 koutput impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9760 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9760 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
5. The current output(s) of the AD9760 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

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AD9760* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
AD9760 Evaluation Board
REFERENCE MATERIALS
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
Digital to Analog Converters ICs Solutions Bulletin
DOCUMENTATION
Application Notes
AN-237: Choosing DACs for Direct Digital Synthesis
AN-320A: CMOS Multiplying DACs and Op Amps Combine
to Build Programmable Gain Amplifier, Part 1
AN-414: Low Cost, Low Power Devices for HDSL
Applications
AN-420: Using the AD9708/AD9760/AD9701/AD9764-EB
Evaluation Board
AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
AD9760: 10-Bit, 125 MSPS+ TxDAC® D/A Converter Data
Sheet
DESIGN RESOURCES
AD9760 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD9760 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
TOOLS AND SIMULATIONS
AD9760 IBIS Models
DOCUMENT FEEDBACK
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AD9760/AD9760-50–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min Typ Max
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
MONOTONICITY
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
10
–1.0 ± 0.5 +1.0
–0.5
± 0.25
+0.5
Guaranteed Over Specified Temperature Range
–0.025
–10
–10
2.0
–1.0
±2
±1
100
5
+0.025
+10
+10
20.0
1.25
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.08 1.20 1.32
100
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o CCOMP1)4
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0.1
1
1.4
0
± 50
± 100
± 50
1.25
POWER SUPPLY
Supply Voltages
AVDD5
DVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)6
Supply Current Sleep Mode (IAVDD)
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (3 V, IOUTFS = 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
2.7
2.7
–0.04
–0.025
5.0
5.0
25
3
140
190
45
5.5
5.5
30
5
8.5
175
+0.04
+0.025
OPERATING RANGE
–40
+85
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3Use an external buffer amplifier to drive any external load.
4Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6Measured at fCLOCK = 50 MSPS and fOUT = 1.0 MHz.
7Measured as unbuffered voltage output into 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
Units
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
k
pF
V
nA
V
M
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
–2– REV. B

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AD9760
DYNAMIC SPECIFICATIONS (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted)
Model
Parameter
AD9760
Min Typ Max
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
125
35
1
5
2.5
2.5
50
30
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MSPS; fOUT = 2.51 MHz
fCLOCK = 50 MSPS; fOUT = 5.02 MHz
fCLOCK = 50 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 2.51 MHz
fCLOCK = 100 MSPS; fOUT = 5.04 MHz
fCLOCK = 100 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 40.4 MHz
Spurious-Free Dynamic Range within a Window
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MHz; fOUT = 2.00 MHz
fCLOCK = 100 MHz; fOUT = 2.00 MHz
70
68
74
72
73
73
68
55
74
68
60
52
78
76
76
–76 –73
–71
–71
–71
NOTES
1Measured single ended into 50 load.
Specifications subject to change without notice.
AD9760-50
Min Typ Max
50 60
35
1
5
2.5
2.5
50
30
68 73
66
73
68
55
N/A
N/A
N/A
N/A
72 78
70
76
N/A
–76 –70
–68
–71
N/A
Units
MSPS
ns
ns
pV-s
ns
ns
pA/Hz
pA/Hz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
REV. B
–3–

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AD9760
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
Parameter
Min Typ Max
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
Specification subject to change without notice.
3.5 5
2.1 3
0 1.3
0 0.9
–10 +10
–10 +10
5
2.0
1.5
3.5
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
DB0DB9
CLOCK
IOUTA OR
IOUTB
tS tH
tLPW
tPD tST
0.1%
0.1%
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect to Min
Max
Units
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
COMP1, COMP2
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
–0.3 +6.5
V
–0.3 +6.5
V
–0.3 +0.3
V
–6.5 +6.5
V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–1.0 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 +0.3
V
+150
°C
–65 +150
°C
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Package
Descriptions Options
AD9760AR
AD9760ARU
AD9760AR50
AD9760ARU50
AD9760-EB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
28-Lead 300 mil R-28
SOIC
28-Lead 170 mil RU-28
TSSOP
28-Lead 300 mil R-28
SOIC
28-Lead 170 mil RU-28
TSSOP
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil (7.5 mm) SOIC
θJA = 71.4°C/W
θJC = 23°C/W
28-Lead 170 mil (4.4 mm) TSSOP
θJA = 97.9°C/W
θJC = 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. B