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DATASHEET
X9221A
64 Taps, 2-Wire Serial Bus Dual Digitally Controlled Potentiometer (XDCP™)
FN8163
Rev 2.00
August 30, 2006
FEATURES
• Two XDCPs in one package
• 2-wire serial interface
• Register oriented format, 8 registers total
—Directly write wiper position
—Read wiper position
—Store as many as four positions per pot
• Instruction format
—Quick transfer of register contents to resistor
array
• Direct write cell
—Endurance–100,000 writes per bit per register
• Resistor array values
—2k, 10k, 50k
• Resolution: 64 taps each pot
• 20 Ld plastic DIP and 20 Ld SOIC packages
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9221A integrates two digitally controlled potenti-
ometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non-
volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
8
Data
Pot 0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Register
Array
Pot 1
VH1/RH1
VL1/RL1
VW1/RW1
FN8163 Rev 2.00
August 30, 2006
Page 1 of 15

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X9221A
Ordering Information
PART NUMBER
X9221AYS
PART MARKING
X9221AYS
VCC LIMITS
(V)
5 ±10%
RTOTAL (k)
2
TEMP
RANGE (°C)
PACKAGE
0 to +70 20 Ld SOIC (300MIL)
PKG.
DWG. #
MDP0027
X9221AYSZ (Note) X9221AYS Z
0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AYSI*
X9221AYSI
-40 to +85 20 Ld SOIC (300MIL)
MDP0027
X9221AYSIZ* (Note) X9221AYSI Z
-40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AWS*
X9221AWS
10 0 to +70 20 Ld SOIC (300MIL)
MDP0027
X9221AWSZ* (Note) X9221AWS Z
0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AWSI*
X9221AWSI
-40 to +85 20 Ld SOIC (300MIL)
MDP0027
X9221AWSIZ* (Note) X9221AWSI Z
-40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
X9221AUP
X9221AUP
50 0 to +70 20 Ld PDIP
MDP0031
X9221AUPZ (Note) X9221AUPZ
0 to +70 20 Ld PDIP (Pb-Free)
MDP0031
X9221AUPI
X9221AUPI
-40 to +85 20 Ld PDIP
MDP0031
X9221AUPIZ (Note) X9221AUPIZ
-40 to +85 20 Ld PDIP (Pb-Free)
MDP0031
X9221AUSI*
X9221AUSI
-40 to +85 20 Ld SOIC (300MIL)
MDP0027
X9221AUSIZ* (Note) X9221AUSI Z
-40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Potentiometer Pins
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9221A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs. An open drain output requires the use of
a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
Address
The Address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9221A
VH/RH(VH0/RH0-VH1/RH1), VL/RL (VL0/RL0-VL1/RL1)
The VH/RH and VL/RL inputs are equivalent to the termi-
nal connections on either end of a mechanical potenti-
ometer.
VW/RW (VW0/RW0-VW1/RW1)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
PIN CONFIGURATION
VW0/RW0
VL0/RL0
VH0/RL0
A0
A2
VW1/RW1
VL1/RL1
VH1/RH1
SDA
VSS
DIP/SOIC
1 20
2 19
3 18
4 17
5 X9221A 16
6 15
7 14
8 13
9 12
10 11
VCC
RES
RES
RES
A1
A3
SCL
RES
RES
RES
FN8163 Rev 2.00
August 30, 2006
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X9221A
PIN NAMES
Symbol
SCL
SDA
A0–A3
VH0/RH0-VH1/RH1,
VL0/RH0-VL1/RL0
VW0/RW0-VW1/RW1
RES
Description
Serial Clock
Serial Data
Address
Potentiometers
(terminal equivalent)
Potentiometers
(wiper equivalent)
Reserved (Do not connect)
PRINCIPLES OF OPERATION
The X9221A is a highly integrated microcircuit incorpo-
rating two resistor arrays, their associated registers and
counters and the serial interface logic providing direct
communication between the host and the XDCP potenti-
ometers.
Serial Interface
The X9221A supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There-
fore, the X9221A will be considered a slave device in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (tLOW). SDA state changes during SCL
HIGH are reserved for indicating start and stop condi-
tions.
Start Condition
All commands to the X9221A are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9221A continuously
monitors the SDA and SCL lines for the start condition,
and will not respond to any command until this condition
is met.
Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data. See Figure 7.
The X9221A will respond with an acknowledge after rec-
ognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9221A will respond with a final acknowledge.
Array Description
The X9221A is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical potenti-
ometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identi-
fier (refer to Figure 1 below). For the X9221A this is fixed
as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
0 1 0 1 A3 A2 A1 A0
Device Address
FN8163 Rev 2.00
August 30, 2006
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