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DATASHEET
X9250
Low Noise/Low Power/SPI Bus/256 Taps Quad Digitally Controlled
Potentiometers (XDCP™)
FN8165
Rev.3.00
August 29, 2006
FEATURES
• Four potentiometers in one package
• 256 resistor taps/pot - 0.4% resolution
• SPI serial interface
• Wiper resistance, 40typical @ VCC = 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100k, 50ktotal pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9251
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Pot 0
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VW3/RW3
VH3/RH3
VL3/RH3
FN8165 Rev.3.00
August 29, 2006
Page 1 of 20

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X9250
Ordering Information
PART NUMBER
X9250TS24I
PART
MARKING
X9250TS I
VCC LIMITS (V)
5 ±10%
POTENTIOMETER
ORGANIZATION (k)
100
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
-40 to +85 24 Ld SOIC (300 mil) M24.3
X9250TS24IZ (Note) X9250TS ZI
-40 to +85
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250TV24I
X9250TV I
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ (Note) X9250TV ZI
-40 to +85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250US24
X9250US
50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9250US24Z (Note)
X9250US Z
0 to +70
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250US24I
X9250US I
-40 to +85 24 Ld SOIC (300 mil) M24.3
X9250US24IZ (Note) X9250US ZI
-40 to +85
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250UV24I
X9250UV I
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24IZ (Note) X9250UV ZI
-40 to +85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250TS24-2.7
X9250TS F
-2.7 to 5.5
100
0 to +70 24 Ld SOIC (300 mil) M24.3
X9250TS24Z-2.7 (Note) X9250TS ZF
0 to +70
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250TS24I-2.7*
X9250TS G
-40 to +85 24 Ld SOIC (300 mil) M24.3
X9250TS24IZ-2.7*
(Note)
X9250TS ZG
-40 to +85
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250TV24I-2.7
X9250TV G
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ-2.7 (Note) X9250TV ZG
-40 to +85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250US24-2.7*
X9250US F
50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9250US24Z-2.7* (Note) X9250US ZF
0 to +70
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250US24I-2.7
X9250US G
-40 to +85 24 Ld SOIC (300 mil) M24.3
X9250US24IZ-2.7 (Note) X9250US ZG
-40 to +85
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250UV24-2.7
X9250UV F
0 to +70
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24Z-2.7 (Note) X9250UV ZF
0 to +70
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250UV24I-2.7
X9250UV G
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24IZ-2.7 (Note) X9250UV ZG
-40 to +85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8165 Rev.3.00
August 29, 2006
Page 2 of 20

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X9250
PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle, data
is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9250, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
Device Address (A0 - A1)
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9250. A maximum of 4 devices may occupy the SPI
serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
VW/RW (VW0/RW0 - VW3/RW3)
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
S0
A0
VW3/RW3
VH3/RH3
VL3/RL3
V+
VCC
VL0/RL0
VH0/RH0
VW0/RW0
CS
WP
SOIC/TSSOP
1 24
2 23
3 22
4 21
5 20
6 19
7 X9250 18
8 17
9 16
10 15
11 14
12 13
HOLD
SCK
VL2/RL2
VH2/RL2
VW2/RW2
V–
VSS
VW1/RW1
VH1/RH1
VL1/RL1
A1
SI
PIN NAMES
Symbol
SCK
SI, SO
A0-A1
VH0/RH0–VH3/RH3,
VL0/RL0–VL3/RL3
VW0/RW0–VW3/RW3
WP
V+,V-
VCC
VSS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
FN8165 Rev.3.00
August 29, 2006
Page 3 of 20