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DATASHEET
X9252
Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface Quad
Digitally-Controlled (XDCP™) Potentiometer
FN8167
Rev 3.00
July 24, 2014
The X9252 integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented
using 255 resistive elements in a series array. Between each
pair of elements are tap points connected to wiper terminals
through switches. The position of each wiper on the array is
controlled by the user through the Up/Down (U/D) or 2-wire
bus interface. The wiper of each potentiometer has an
associated volatile Wiper Counter Register (WCR) and four
nonvolatile Data Registers (DRs) that can be directly written
to and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array through the
switches. At power-up, the device recalls the contents of the
default data registers DR00, DR10, DR20, DR30, to the
corresponding WCR.
Each DCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including the programming of bias voltages, the
implementation of ladder networks, and three resistor
programmable networks.
Features
• Quad Solid State Potentiometer
• 256 Wiper Tap Points-0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Up/Down Interface for Individual Potentiometers
• Wiper Resistance: 40Typical
• NonVolatile Storage of Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power-Up.
• Standby Current < 100µA Max
• Maximum Wiper Current: 3mA
• VCC: 2.7V to 5.5V Operation
• 2.8kand 10kVersion of Total Pot Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 24 Ld TSSOP
• Pb-Free (RoHS Compliant)
Pinout
X9252
(24 LD TSSOP)
TOP VIEW
DS0
A0
RW3
RH3
RL3
U/D
VCC
RL0
RH0
RW0
A2
WP
1
2
3
4
5
6
7
8
9
10
11
12
24 DS1
23 SCL
22 RL2
21 RH2
20 RW2
19 CS
18 VSS
17 RW1
16 RH1
15 RL1
14 A1
13 SDA
FN8167 Rev 3.00
July 24, 2014
Page 1 of 19

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X9252
Ordering Information
PART
NUMBER
(Notes 1, 2)
X9252YV24IZ-2.7
PART
MARKING
X9252YV ZG
RTOTAL
(k)
2.8
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
-40 to +85 24 Ld TSSOP (4.4mm)
PKG.
DWG. #
M24.173
X9252WV24IZ-2.7
X9252WV ZG
10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for X9252. For more information on MSL please see tech brief TB363
Functional Diagram
VCC
A2
A1
A0
SDA
SCL
DS0
2-Wire
Interface
Up-Down
Interface
POWER-UP,
INTERFACE
CONTROL
AND
STATUS
DS1
CS
U/D
VSS
RH0
RH1
RH2
RH3
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
WP
RW0 RL0
RW1 RL1
RW2 RL2
RW3 RL3
Pin Descriptions
PIN #
1, 24
2, 14, 11
3
4
5
6
7
8
9
10
12
13
15
16
17
18
SYMBOL
DS0, DS1
A0, A1, A2
RW3
RH3
RL3
U/D
VCC
RL0
RH0
RW0
WP
SDA
RL1
RH1
RW1
VSS
DESCRIPTION
DCP select for Up/Down interface.
Device address for 2-wire bus.
Wiper terminal of DCP3.
High terminal of DCP3.
Low terminal of DCP3.
Increment/decrement for up/down interface.
System supply voltage
Low terminal of DCP0.
High terminal of DCP0.
Wiper terminal of DCP0.
Hardware write protect
Serial data input/output for 2-wire bus.
Low terminal of DCP1.
High terminal of DCP1.
Wiper terminal DCP1.
System ground
FN8167 Rev 3.00
July 24, 2014
Page 2 of 19

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X9252
Pin Descriptions (Continued)
PIN #
19
20
21
22
23
SYMBOL
CS
RW2
RH2
RL2
SCL
Chip select for Up/Down interface.
Wiper terminal of DCP2.
High terminal of DCP2.
Low terminal of DCP2.
Serial clock for 2-wire bus.
DESCRIPTION
Pin Descriptions
Bus Interface Pins
Serial Data Input/Output (SDA)
The SDA is a bidirectional serial data input/output pin for the 2-
wire interface. It receives device address, operation code, wiper
register address and data from a 2-wire external master device
at the rising edge of the serial clock SCL, and it shifts out data
after each falling edge of the serial clock SCL.
SDA requires an external pull-up resistor, since it’s an open
drain output.
Serial Clock (SCL)
This input is the serial clock of the 2-wire and Up/Down
interface.
Device Address (A0, A1, A2)
The Address inputs are used to set the least significant 3 bits of
the 8-bit 2-wire interface slave address. A match in the slave
address serial data stream must be made with the Address input
pins in order to initiate communication with the X9252. A
maximum of 8 devices may occupy the 2-wire serial bus.
Chip Select (CS)
When the CS pin is low, increment or decrement operations
are possible using the SCL and U/D pins. The 2-wire interface
is disabled at this time. When CS is high, the 2-wire interface is
enabled.
Up or Down Control (U/D)
The U/D input pin is held HIGH during increment operations
and held LOW during decrement operations.
DCP Select (DS1 and DS0)
The DS1 and DS0 select one of the four DCPs for an Up/Down
interface operation.
Hardware Write Protect Input (WP)
When the WP pin is set low, “write” operations to nonvolatile
DCP Data Registers are disabled. This includes both 2-wire
interface nonvolatile “Write”, and Up/Down interface “Store”
operations.
DCP Pins
RH0, RL0, RH1, RL1, RH2, RL2, RH3, and RL3
These pins are equivalent to the terminal connections on
mechanical potentiometers. Since there are 4 DCPs, there is
one set of RH and RL for each DCP.
RW0, RW1, RW2, and RW3
The wiper pins are equivalent to the wiper terminal of
mechanical potentiometers. Since there are four DCPs, there
are 4 RW pins.
FN8167 Rev 3.00
July 24, 2014
Page 3 of 19