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DATASHEET
X9258
Low Noise/Low Power/2-Wire Bus/256 Taps Quad Digital Controlled
Potentiometers (XDCP™)
FN8168
Rev 6.00
December 15, 2011
The X9258 integrates 4 digitally controlled potentiometers
(XDCP™) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 non-volatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power-up
recalls the contents of DR0 to the WCR.
The XDCP™ can be used as a three-terminal potentiometer
or as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four potentiometers in one package
• 256 resistor taps/potentiometer................. 0.4% resolution
• 2-wire serial interface
• Wiper resistance, 40Ωtypical @ V+ = 5V, V- = -5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of wiper position
• Standby current <5µA max (total package)
• Power supplies
- VCC = 2.7V to 5.5V
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• 100kΩ, 50kΩtotal potentiometer resistance
• High reliability
- Endurance: 100,000 data changes per bit per register
- Register data retention . . . . . . . . . . . . . . . . . . 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9259
• Pb-free (RoHS compliant)
Block Diagram
VCC
VSS
V+
V-
WP
SCL
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
8
DATA
R0 R1
WIPER
COUNTER
REGISTER
R2 R3
(WCR)
POT 0
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1 WIPER
COUNTER
REGISTER
R2 R3
(WCR)
RESISTOR
ARRAY
POT 2
VH2/RH2
VL2/RL2
VW2/RW2
VW1/RW1
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 1
VH1/RH1
VL1/RL1
VW3/RW3
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 3
VH3/RH3
VL3/RL3
FN8168 Rev 6.00
December 15, 2011
Page 1 of 19

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X9258
X9258
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
POTENTIOMETER TEMPERATURE
VCC LIMITS ORGANIZATION
(V) (kΩ)
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
X9258US24Z (Note 1)
X9258US Z
5 ±10
50
0 to +70 24 Ld SOIC (300 mil)
M24.3
X9258US24IZ (Note 1) X9258US ZI
-40 to +85 24 Ld SOIC (300 mil)
M24.3
X9258UV24IZ
X9258UV ZI
-40 to +85 24 Ld TSSOP (4.4mm)
MDP0044
X9258TS24Z
X9258TS Z
100
0 to +70 24 Ld SOIC (300 mil)
M24.3
X9258TS24IZ (Note 1) X9258TS ZI
-40 to +85 24 Ld SOIC (300 mil)
M24.3
X9258US24Z-2.7 (Note 1) X9258US ZF
2.7 to 5.5
50
0 to +70 24 Ld SOIC (300 mil)
M24.3
X9258US24IZ-2.7 (Note 1) X9258US ZG
-40 to +85 24 Ld SOIC (300 mil)
M24.3
X9258UV24IZ-2.7
X9258UV ZG
-40 to +85 24 Ld TSSOP (4.4mm)
MDP0044
X9258TS24Z-2.7 (Note 1) X9258TS ZF
100
0 to +70 24 Ld SOIC (300 mil)
M24.3
X9258TS24IZ-2.7 (Note 1) X9258TS ZG
-40 to +85 24 Ld SOIC (300 mil)
M24.3
X9258TV24IZ-2.7
X9258TV ZG
-40 to +85 24 Ld TSSOP (4.4mm)
MDP0044
X9258TV24Z-2.7
X9258TV ZF
0 to +70 24 Ld TSSOP (4.4mm)
MDP0044
NOTES:
1. Add “T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9258. For more information on MSL please see tech brief TB363.
FN8168 Rev 6.00
December 15, 2011
Page 2 of 19

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X9258
Pinout
X9258
X9258
(24 LD SOIC, TSSOP)
TOP VIEW
NC
A0
VW3/RW3
VH3/RH3
VL3/RL3
V+
VCC
VL0/RL0
VH0/RH0
VW0/RW0
A2
WP
1
2
3
4
5
6
X9258
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
VL2/RL2
VH2/RH2
VW2/RW2
V–
VSS
VW1/RW1
VH1/RH1
VL1/RL1
A1
SDA
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the X9258.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to “Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors” on page 10.
DEVICE ADDRESS (A0 - A3)
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3)
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW/RW (VW0/RW0 - VW3/RW3)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for the
DCP analog section.
Pin Names
SYMBOL
SCL
SDA
A0 thru A3
VH0/RH0 thru VH3/RH3,
VL0/RL0 thru VL3/RL3
VW0/RW0 thru VW3/RW3
WP
V+, V-
VCC
VSS
NC
DESCRIPTION
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometers Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection (Allowed)
Principles Of Operation
The X9258 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and
the serial interface logic providing direct communication
between the host and the DCP potentiometers.
Serial Interface (2-Wire)
The X9258 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9258 will be considered a slave
device in all applications.
FN8168 Rev 6.00
December 15, 2011
Page 3 of 19