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DATASHEET
X9259
Single Supply/Low Power/256-Tap/2-Wire Bus Quad Digitally-Controlled
(XDCP™) Potentiometers
FN8169
Rev 6.00
December 12, 2014
The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four separate potentiometers in one package
• 256 resistor taps–0.4% resolution
• 2-wire serial interface for write, read, and
transfer operations of the potentiometer
• Wiper resistance: 100Ω typical at VCC = 5V
• 4 nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max
• VCC: 2.7V to 5.5V operation
• 50kΩ version of total resistance
• Endurance: 100,000 data changes per bit per register
• 100 year data retention
• Single supply version of X9258
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-Free (RoHS compliant)
Functional Diagram
VCC
RH0
RH1
RH2
RH3
A3
A2
A1
A0
SDA
SCL
2-WIRE
INTERFACE
POWER UP,
INTERFACE
CONTROL
AND
STATUS
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
VSS
WP
RW0 RL0
RW1 RL1
RW2 RL2
RW3 RL3
FN8169 Rev 6.00
December 12, 2014
Page 1 of 21

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X9259
Ordering Information
PART NUMBER
(Notes 1, 3)
PART
MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
X9259US24Z (Note 2)
X9259US Z
5 ±10%
50
0 to +70
24 Ld SOIC
M24.3
X9259UV24Z
X9259UV Z
0 to +70
24 Ld TSSOP
M24.173
X9259US24IZ (Note 2)
X9259US ZI
-40 to +85
24 Ld SOIC
M24.3
X9259UV24IZ (Note 2)
X9259UV ZI
-40 to +85
24 Ld TSSOP
M24.173
X9259US24Z-2.7 (Note 2) X9259US ZF
2.7 to 5.5
0 to +70
24 Ld SOIC
M24.3
X9259US24IZ-2.7 (Note 2) X9259US ZG
-40 to +85
24 Ld SOIC
M24.3
X9259UV24Z-2.7
X9259UV ZF
0 to +70
24 Ld TSSOP
M24.173
X9259UV24IZ-2.7 (Note 2) X9259UV ZG
-40 to +85
24 Ld TSSOP
M24.173
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add "T1" suffix for tape and reel.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9259. For more information on MSL, please see tech brief TB363.
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators
and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent
systems
FN8169 Rev 6.00
December 12, 2014
Page 2 of 21

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X9259
Pin Configuration
X9259
24 LD SOIC/TSSOP
TOP VIEW
DNC
A0
RW3
RH3
RL3
NC
VCC
RL0
RH0
RW0
A2
WP
1
2
3
4
5
6
X9259
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
A1
SDA
Pin Descriptions
PIN PIN
# NAME
DESCRIPTION
2 A0 Device Address for 2-wire bus. (See Note 4)
3
RW3
Wiper Terminal of DCP3
4 RH3 High Terminal of DCP3
5 RL3 Low Terminal of DCP3
7 VCC System Supply Voltage
8 RL0 Low Terminal of DCP0
9 RH0 High Terminal of DCP0
10
RW0
Wiper Terminal of DCP0
11 A2 Device Address for 2-wire bus. (See Note 4)
12 WP Hardware Write Protect – Active Low
13 SDA Serial Data Input/Output for 2-wire bus.
14 A1 Device Address for 2-wire bus. (See Note 4)
15 RL1 Low Terminal of DCP1
16 RH1 High Terminal of DCP1
17
RW1
Wiper Terminal of DCP1
18 VSS System Ground
20
RW2
Wiper Terminal of DCP2
21 RH2 High Terminal of DCP2
22 RL2 Low Terminal of DCP2
23 SCL Serial Clock for 2-wire bus.
24 A3 Device Address for 2-wire bus. (See Note 4)
6, 19
NC No Connect
1 DNC Do Not Connect
NOTE:
4. A0 through A3 Device address pins must be tied to a logic level.
FN8169 Rev 6.00
December 12, 2014
Page 3 of 21