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a
14-Bit, 125 MSPS
TxDAC® D/A Converter
AD9764
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent SFDR and IMD
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 190 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
ADSL/HFC Modems
Instrumentation
PRODUCT DESCRIPTION
The AD9764 is the 14-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, is specifically opti-
mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, providing an upward or downward compo-
nent selection path based on performance, resolution and cost.
The AD9764 offers exceptional ac and dc performance while
supporting update rates up to 125 MSPS.
The AD9764’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW with a slight degradation in performance
by lowering the full-scale current output. Also, a power-down
mode reduces the standby power dissipation to approximately
25 mW.
The AD9764 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer-
ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.
The AD9764 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 koutput impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
0.1F
RSET
+5V
CLOCK
REFLO
+1.20V REF
REFIO
FS ADJ
COMP1 AVDD ACOM
50pF
AD9764
CURRENT
SOURCE
ARRAY
0.1F
COMP2
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
SLEEP
LATCHES
DIGITAL DATA INPUTS (DB13–DB0)
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9764 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9764 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9764 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9764 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9764 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9764 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond that previously attainable by higher power/cost
bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9764 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V, and
a wide full-scale current adjustment span of 2 mA to 20 mA,
allows the AD9764 to operate at reduced power levels.
5. The current output(s) of the AD9764 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 1999-2016

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AD9764* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD9764 Evaluation Board
Documentation
Application Notes
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-320A: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifier, Part 1
• AN-420: Using the AD9708/AD9760/AD9701/AD9764-EB
Evaluation Board
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
• AD9764: 14-Bit, 125 MSPS TxDAC® D/A Converter Data
Sheet
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD9764 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9764 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

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AD9764–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min Typ Max
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
TA = +25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = +25°C
TMIN to TMAX
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
14
–4.5
–6.5
–2.5
–4.5
–0.025
–2
–7
2.0
–1.0
± 2.5
± 1.5
±1
±1
100
5
+4.5
+6.5
+2.5
+4.5
+0.025
+2
+7
20.0
1.25
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.08 1.20 1.32
100
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o CCOMP1)4
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0.1
1
1.4
0
± 50
± 100
± 50
1.25
POWER SUPPLY
Supply Voltages
AVDD5
DVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)6
Supply Current Sleep Mode (IAVDD)
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (3 V, IOUTFS = 2 mA)
Power Supply Rejection Ratio8—AVDD
Power Supply Rejection Ratio8—DVDD
2.7
2.7
–0.4
–0.025
5.0
5.0
25
1.5
5.0
133
190
45
5.5
5.5
30
4
8.5
170
+0.4
+0.025
OPERATING RANGE
–40
+85
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3Use an external buffer amplifier to drive any external load.
4Reference bandwidth is a function of external cap at COMP1 pin and signal level.
5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.
7Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
8± 5% Power supply variation.
Specifications subject to change without notice.
Units
Bits
LSB
LSB
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
k
pF
V
nA
V
M
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
–2– REV. C

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AD9764
DYNAMIC SPECIFICATIONS (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
0 dBFS Output
TA = +25°C
TMIN to TMAX
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 2.51 MHz
fCLOCK = 50 MSPS; fOUT = 5.02 MHz
fCLOCK = 50 MSPS; fOUT = 20.2 MHz
Spurious-Free Dynamic Range within a Window
fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MHz; fOUT = 2.00 MHz
fCLOCK = 100 MHz; fOUT = 2.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLOCK = 20 MSPS; fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
NOTES
1Measured single-ended into 50 load.
Specifications subject to change without notice.
Min
125
75
73
78
76
Typ Max
35
1
5
2.5
2.5
50
30
82
85
77
70
80
77
70
58
89
84
84
–78 –74
–72
–75
–75
73
76
73
64
Units
MSPS
ns
ns
pV-s
ns
ns
pA/Hz
pA/Hz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
REV. C
–3–

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AD9764
DIGITAL SPECIFICATIONS
Parameter
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
Specifications subject to change without notice.
DB0–DB13
CLOCK
IOUTA
OR
IOUTB
Min Typ
3.5 5
2.1 3
0
0
–10
–10
5
2.0
1.5
3.5
tS tH
tLPW
tPD
tST
0.1%
0.1%
Figure 1. Timing Diagram
Max
1.3
0.9
+10
+10
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect to Min
Max
Units
ORDERING GUIDE
AVDD
ACOM
–0.3 +6.5
V
DVDD
DCOM
–0.3 +6.5
V
ACOM
DCOM
–0.3 +0.3
V
AVDD
DVDD
–6.5 +6.5
V
CLOCK, SLEEP
DCOM
–0.3 DVDD + 0.3 V
Digital Inputs
DCOM
–0.3 DVDD + 0.3 V
IOUTA, IOUTB
COMP1, COMP2
ACOM
ACOM
–1.0 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
REFIO, FSADJ
ACOM
–0.3 AVDD + 0.3 V
REFLO
ACOM
–0.3 +0.3
V
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
+150
–65 +150
+300
°C
°C 1 RW = Small Outline IC, RU = TSSOP.
°C 2 Z = RoHS Compliant Part.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOIC
θJA = 71.4° C/W
θJC = 23° C/W
28-Lead TSSOP
CAUTION
θJA = 97.9° C/W
θJC = 14.0° C/W
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD9764 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
–4– REV. C