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Dual Matched Broadband RF
DVGA 600MHz to 2700MHz
F0440
Datasheet
Description
This document describes the specifications for the F0440
600MHz to 2700MHz Dual RF Digital Variable Gain Amplifier
designed for use in receivers.
F0440 Dual RF DVGA provides two independent receiver paths
each with 11.6dB typical maximum gain and 4.7dB noise figure in
the lowband configuration designed to operate with a single +5V
supply. For each path Gain control is split into 3 separate
attenuators; DSA0 is a single 6dB step using a single control pin,
DSA1 includes 23dB SPI-controlled gain adjustment in 1dB steps,
and DSA2 includes 18dB attenuation in 6dB steps controlled
using two control pins. F0440 offers +40dBm nominal output IP3
using 245mA total ICC.
This device is packaged in a 6mm x 6mm, 36-pin TQFN with 50
ohm single-ended RF input and RF output impedances for ease
of integration into the signal-path lineup for each of the two paths.
Competitive Advantage
High Reliability
High Linearity
Low DC current
Zero DistortionTM technology
GlitchFreeTM technology
Typical Applications
Multi-mode, Multi-carrier Receivers
PCS1900 Base Stations
DCS1800 Base Stations
WiMAX and LTE Base Stations
UMTS/WCDMA 3G Base Stations
PHS/PAS Base Stations
Distributed Antenna Systems
Digital Radio
Table 1. Typical Band Performance Summary
RF Frequency (MHz)
Max Gain (dB)
NF @ max gain (dB)
OIP3 @ max gain (dBm)
OP1dB @ max gain (dBm)
DC current (mA)
Power Dissipation (mW)
900
11.6
4.7
+40
+20.2
245
1225
2000
11.4
4.9
+41
+19.8
245
1225
2700
11.6
5.2
+38
+18.9
245
1225
Features
Dual Path RF amp & DSAs for Diversity / MIMO Receivers
RF: 600MHz to 2700MHz
< 2dB overshoot between DSA transitions
11.6dB typical max gain @ 900MHz
DSA0 is a single 6dB coarse step
DSA1 has 23dB total gain range in 1dB steps
DSA2 has 18dB gain range in 6dB steps
+41dBm OIP3 @ 2000MHz
4.7dB Noise Figure @ 900MHz
+5V Supply Voltage
ICC = 245mA
Independent standby: 7mA standby current
SPI interface for DSA1
1-bit control for DSA0
2-bit control for DSA2
50 Ω input and output impedance
Broadband, Internally Matched
6mm x 6mm, 36-pin TQFN package
Block Diagram
Figure 1. Block Diagram
F0440
6dB 23dB
RFIN_A
SPI Data
SPI CSb
SPI CLK
VCTRL0
VCTRL1
VCTRL2
STBY
2
2
2
2
2
Decode
Logic / Bias
RFIN_B
DSA0 DSA1
18dB
RF AMP
DSA2
RFOUT_A
RFOUT_B
6mm x 6mm
© 2020 Renesas Electronics Corporation
1
May 13, 2020

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Pin Assignments
Figure 2. Pin Assignments for 6 x 6 mm 36-TQFN Package – Top View
F0440 Datasheet
F0440 36 35 34 33 32 31 30 29 28
DSA0_A
RFin_A 1
DSA1_A
DSA2_A
GND 2
VCTRL0_A 3
SPI Data 4
SPI Clk 5
VCC 6
De cod e
Logic
Bias
Control
VCTRL0_B 7
GND 8
RFin_B 9
DSA0_B DSA1_B
DSA2_B
10 11 12 13 14 15 16 17 18
27 RFout_A
26 NC
25 VCC
24 Rset
23 VCC
22 RDset
21 VCC
20 NC
19 RFout_B
© 2020 Renesas Electronics Corporation
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May 13, 2020

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F0440 Datasheet
Pin Descriptions
Table 2. Pin Descriptions
Number
1
2, 8, 15, 16,
17, 29, 30,
31
3
4
5
6, 21, 23, 25
7
9
10, 18, 20,
26, 28, 36
11
12
13
14
19
22
24
27
32
33
34
35
Name
RFin_A
GND
VCTRL0_A
SPI Data[a]
SPI Clk[a]
VCC
VCTRL0_B
RFin_B
NC
SPI CSb_B[a]
STBY_B
VCTRL1_B
VCTRL2_B
RFout_B
RDset
Rset
RFout_A
VCTRL2_A
VCTRL1_A
STBY_A
SPI CSb_A[a]
— EP
Description
RF Path A input internally matched to 50 Ω. Must use external DC block.
Ground these pins.
1bit DSA0 6dB attenuator control for path A
Data input: 3.3V or 1.8V CMOS compatible.
Clock input: 3.3V or 1.8V CMOS compatible.
+5V Power Supply. Use bypass capacitors as close to pin as possible.
1bit DSA0 6dB attenuator control for path B
RF Path B input internally matched to 50 Ω. Must use external DC block.
No internal connection. Can be either left open or connected to GND (recommended)
Chip Select bar input path B: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data.
Standby (Low/Open = device power ON, High = device power OFF with SPI still powered ON). A pull-
down resistor connects between input and GND.
See separate attenuation logic table for Path B DSA2.
See separate attenuation logic table for Path B DSA2.
RF output Path B. Use external DC block as close to the pin as possible.
Connect external resistor to GND to optimize amplifier bias. Used with pin 24.
Connect external resistor to GND to optimize amplifier bias. Used with pin 22.
RF output Path A. Use external DC block as close to the pin as possible.
See separate attenuation logic table for Path A DSA2.
See separate attenuation logic table for Path A DSA2.
Standby (Low/Open = device power ON, High = device power OFF with SPI still powered ON). A pull-
down resistor connects between input and GND.
Chip Select bar input path A: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data.
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple
ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground
vias are also required to achieve the noted RF performance.
a. See Serial Control Word section for description.
© 2020 Renesas Electronics Corporation
3
May 13, 2020