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a
LC2MOS
Dual 12-Bit Serial DACPORT®
AD7249
FEATURES
Two 12-Bit CMOS DAC Channels with
On-Chip Voltage Reference
Output Amplifiers
Three Selectable Output Ranges per Channel
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
125 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Low Power Dissipation
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
GENERAL DESCRIPTION
The AD7249 DACPORT contains a pair of 12-bit, voltage-
output, digital-to-analog converters with output amplifiers and
Zener voltage reference on a monolithic CMOS chip. No exter-
nal trims are required to achieve full specified performance.
The output amplifiers are capable of developing +10 V across a
2 kload. The output voltage ranges with single supply opera-
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipolar
± 5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.
Interfacing to the AD7249 is serial, minimizing pin count and
allowing a small package size. Standard control signals allow
interfacing to most DSP processors and microcontrollers. The
data stream consists of 16 bits, DB15 to DB13 are don’t care
bits, the 13th bit (DB12) is used as the channel select bit and
the remaining 12 bits (DB11 to DB0) contain the data to update
the DAC. The 16-bit data word is clocked into the input register
on each falling SCLK edge.
The data format is natural binary in both unipolar ranges, while
either offset binary or twos complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the twos comple-
ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the outputs to be set to a known voltage level.
REFOUT
FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
AD7249
2R
2R
ROFSA
REFIN
AGND
DGND
12-BIT
DAC A
A1
2R
2R
12-BIT
DAC B
A2
INPUT SHIFT REGISTER
VOUTA
ROFSB
VOUTB
SCLK SDIN SYNC BIN/COMP CLR LDAC
The AD7249 features a serial interface which allows easy con-
nection to both microcomputers and 16-bit digital signal proces-
sors with serial ports. The serial data may be applied at rates up
to 2 MHz allowing a DAC update rate of 125 kHz.
The AD7249 is fabricated on linear compatible CMOS
(LC2MOS), an advanced, mixed technology process. It is pack-
aged in 16-lead DIP and 16-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. Two complete 12-bit DACPORTs
The AD7249 contains two complete voltage output, 12-bit
DACs in both 16-lead DIP and SOIC packages.
2. Single or dual supply operation
3. Minimum 3-wire interface to most DSP processors
4. DAC update rate—125 kHz
DACPORT is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

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AD7249–SPECIFICATIONS (VDD = +12 V to +15 V,1 VSS = O V or –12 V to –15 V,1 AGND = DGND = O V, REFIN =
+5 V, RL = 2 k, CL = 100 pF to AGND. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version2 B Version2 S Version2 Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy3
Differential Nonlinearity3
Unipolar Offset Error3
12
±1
± 0.9
±5
Bipolar Zero Error3
±6
Full-Scale Error3, 4
±6
Full-Scale Temperature Coefficient ± 5
12
± 1/2
± 0.9
±5
±5
±6
±5
12
±1
± 0.9
±6
±7
±7
±5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
ppm of FSR/°C typ
Guaranteed Monotonic
VSS = 0 V or –12 V to –15 V1; DAC
Latch Contents All 0s
VSS = –12 V to –15 V1
DAC Latch Contents All 0s
REFERENCE OUTPUT
REFOUT
Reference Temperature Coefficient
Reference Load Change
(VREFOUT vs. IL)
4.95/5.05
± 25
–1
4.95/5.05
± 25
–1
4.95/5.05
± 30
–1
V min/V max
ppm/°C typ
mV max
Reference Load Current (IL)
Change (0 µA–100 µA)
REFERENCE INPUT
Reference Input Range, REFIN
Input Current
4.95/5.05
5
4.95/5.05
5
4.95/5.05
5
V min/V max
µA max
5 V ± 1%
DIGITAL INPUTS
Input High Voltage, VINH 2.4 2.4 2.4 V min
Input Low Voltage, VINL
0.8 0.8 0.8 V max
Input Current
IIN
Input Capacitance5
± 1 ± 1 ± 1 µA max VIN = 0 V to VDD
8 8 8 pF max
ANALOG OUTPUTS
Output Range Resistor,
ROFSA & ROFSB
Output Voltage Ranges6
Output Voltage Ranges6
DC Output Impedance
15/30
+5, +10
+5, +10, ± 5
0.5
15/30
+5, +10
+5, +10, ± 5
0.5
15/30
+5, +10
+5, +10, ± 5
0.5
kmin/ max
V
V
typ
Single Supply; VSS = 0 V
Dual Supply; VSS = –12 V or –15 V
AC CHARACTERISTICS5
Voltage Output Settling-Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse3
Digital Feedthrough3
Digital Crosstalk3
10
10
30
10
10
Settling Time to Within
± 1/2 LSB of Final Value
10 10 µs max
Typically 3 µs
10 10 µs max
Typically 5 µs
30
30
nV secs typ
1 LSB Change Around
Major Carry
10 10 nV secs typ
10 10 nV secs typ
POWER REQUIREMENTS
VDD Range
VSS Range (Dual Supplies)
IDD
ISS (Dual Supplies)
+10.8/+16.5
–10.8/–16.5
15
5
+11.4/+15.75 +11.4/+15.75 V min/V max
–11.4/–15.75 –11.4/–15.75 V min/V max
15 15 mA max
5 5 mA max
For Specified Performance Unless
Otherwise Stated
For Specified Performance Unless
Otherwise Stated
Output Unloaded; Typically 11 mA
Output Unloaded; Typically 3 mA
NOTES
1Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%.
2Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3See Terminology.
4Measured with respect to REFIN and includes unipolar/bipolar offset error.
5Guaranteed by design not production tested.
60 V to 10 V output range available only with VDD 14.25 V.
Specifications subject to change without notice.
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AD7249
TIMING CHARACTERISTICS1, 2 (VDD = +12 V to +15 V,3 VSS = 0 V or –12 V to –15 V,3 AGND = DGND = 0 V, RL = 2 k,
CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at TMIN to TMAX
(All Versions)
Unit
Conditions/Comments
t14 200
t2 15
t3 50
t4 0
t5 150
t6 0
t7 20
t8 0
t9 50
t10 20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SYNC to SCLK Falling Edge Setup Time
SYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC High to LDAC Low
LDAC Pulsewidth
LDAC High to SYNC Low
CLR Pulsewidth
SYNC High Time
NOTES
1Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.
2See Figure 8.
3Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%.
4SCLK Mark/Space Ratio range is 45/55 to 55/45.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to AGND, DGND . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND, DGND . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VOUTA,
2
B
to
AGND
............
VSS – 0.3 V to VDD + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
REFIN to AGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +117°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C
Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C
Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature (Soldering)
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7249 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
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AD7249
Pin Mnemonic
11 REFOUT
12 REFIN
13 ROFSB
14 VOUTB
15 AGND
16 CLR
17 BIN/COMP
18 DGND
19 SDIN
10 LDAC
11 SCLK
12 SYNC
13 VDD
14 VOUTA
15 VSS
16 ROFSA
PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS)
Description
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the
part using its internal reference, REFOUT should be connected to REFIN.
Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal
reference voltage for specified operation of the AD7249 is 5 V.
Output Offset Resistor for the amplifier of DAC B. It is connected to VOUTB for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
Analog Ground. Ground reference for all analog circuitry.
Clear, Logic Input. Taking this input low clears both DACs. It sets VOUTA and VOUTB to 0 V in both
unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar
range.
Logic Input. This input selects the data format to be either binary or twos complement. In both uni-
polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar
configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement.
Digital Ground. Ground reference for all digital circuitry.
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling
edge of this signal or alternatively if this line is permanently low, an automatic update mode is se-
lected whereby both DACs are updated on the 16th falling SCLK pulse.
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi-
ness for a new data word.
Positive Power Supply.
Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup-
ply operation or –12 V to –15 V for dual supplies.
Output Offset Resistor for the amplifier of DAC A. It is connected to VOUTA for the +5 V range, to
AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
PIN CONFIGURATIONS
(DIP and SOIC)
REFOUT 1
16 ROFSA
REFIN 2
15 VSS
ROFSB 3
14 VOUTA
VOUTB 4 AD7249 13 VDD
AGND
5
TOP VIEW
(Not to Scale) 12
SYNC
CLR 6
11 SCLK
BIN/COMP 7
10 LDAC
DGND 8
9 SDIN
ORDERING GUIDE
Model
Temperature
Range
Relative
Accuracy
Package
Option
AD7249AN
AD7249BN
AD7249AR
AD7249BR
AD7249SQ1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
± 1 LSB
± 1/2 LSB
± 1 LSB
± 1/2 LSB
± 1 LSB
N-16
N-16
R-16
R-16
Q-16
NOTE
1Available to /883B processing only. Contact your local sales office for military
data sheet.
–4– REV. C

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AD7249
TERMINOLOGY
Bipolar Zero Error
Bipolar Zero Error is the voltage measured at VOUT when the
DAC is configured for bipolar output and loaded with all 0s
(Twos Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at VOUT when the digital
code in the DAC Latch changes, before the output settles to its
final value. It is normally specified as the area of the glitch in
nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (0111 1111 1111 to 1000
0000 0000 or 1000 0000 0000 to 0111 1111 1111).
Digital Feedthrough
This is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7249. It
is measured with LDAC held high.
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
The output amplifier on the AD7249 can have true negative
offsets even when the part is operated from a single +15 V sup-
ply. However, because the negative supply rail (VSS) is 0 V, the
output cannot actually go negative. Instead, when the output
offset voltage is negative, the output voltage sits at 0 V, resulting
in the transfer function shown in Figure 1.
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the
output voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7249 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions, the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from VOUT
with all zeros loaded into the DAC latch, when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
CIRCUIT INFORMATION
D/A Section
The AD7249 contains two 12-bit voltage-mode D/A converters
consisting of highly stable thin film resistors and high-speed
NMOS single-pole, double-throw switches. The simplified
circuit diagram for the DAC section is shown in Figure 2. The
output voltage from the converter has the same polarity as the
reference voltage, REFIN, allowing single supply operation.
ROFS
2R
2R
R RRRR
VOUT
2R 2R 2R
2R 2R 2R
OUTPUT
VOLTAGE
REFIN*
AGND
SHOWN FOR ALL 1s
ON DAC
*BUFFERED REFIN VOLTAGE
Figure 2. D/A Simplified Circuit Diagram
0V
NEGATIVE
OFFSET
DAC CODE
Figure 1. Effect of Negative Offset (Single Supply)
REV. C
–5–