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a
Low Cost, Low Power CMOS
General Purpose Analog Front End
AD73311
FEATURES
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
75 dB ADC SNR
70 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows up to 8 Devices
to Be Connected in Cascade
Single (+2.7 V to +5.5 V) Supply Operation
50 mW Max Power Consumption at 2.7 V
On-Chip Reference
20-Lead SOIC/SSOP Package
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound & Vibration
Data Communications
GENERAL DESCRIPTION
The AD73311 is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70 dB signal-to-noise ratio over
a voiceband signal bandwidth. The final channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital filtering in a DSP engine.
The AD73311 is suitable for a variety of applications in the
speech and telephony area including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.
The gains of the A/D and D/A conversion channels are pro-
grammable over 38 dB and 21 dB ranges respectively. An
on-chip reference voltage is included to allow single supply
operation. A serial port (SPORT) allows easy interfacing of
single or cascaded devices to industry standard DSP engines.
The AD73311 is available in both 20-lead SOIC and SSOP
packages.
AVDD1
FUNCTIONAL BLOCK DIAGRAM
AVDD2
DVDD
VINP
VINN
VOUTP
VOUTN
REFCAP
REFOUT
0/38dB
PGA
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS FILTER
REFERENCE
ANALOG
SIGMA-DELTA
MODULATOR
SWITCHED-
CAPACITOR
LOW-PASS FILTER
1-BIT
DAC
DIGITAL
SIGMA-DELTA
MODULATOR
DECIMATOR
INTERPOLATOR
SERIAL
I/O
PORT
AD73311
AGND1
AGND2
DGND
SDI
SDIFS
SCLK
SDO
SDOFS
SE
MCLK
RESET
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

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AD73311–SPECIFICATIONS1 (AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
FS = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
Parameter
AD73311A
Min Typ Max Unit
Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
1.08 1.2
50
68
1.08 1.2
1
5VEN = 0
1.32 V
ppm/°C 0.1 µF Capacitor Required from
REFCAP to AGND2
1.32 V
Unloaded
k
100 pF
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk
DC Offset
Power Supply Rejection
Group Delay4, 5
Input Resistance at VIN2, 4
1.0954
6.02
1.578
2.85
V p-p
dBm
V p-p
dBm
0.75 0.1
+1.0 dB
1.5 0.5 +0.5 dB
± 0.1 dB
70 76
55 56
61 65
53 54
dB
dB
dB
dB
83
83
78
76
100
70
70
dB
dB
dB
dBm0
dB
20 +15 +50 mV
55 dB
25 µs
25 k6
5VEN = 0, Measured Differentially
5VEN = 0, Measured Differentially
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to 50 dBm0
Refer to Figure 5
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins 1.0 kHz, 100 mV p-p Sine Wave
64 kHz Output Sample Rate
DMCLK = 16.384 MHz
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single Ended
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 6 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 6 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk
1.578
2.85
3.156
3.17
V p-p
dBm
V p-p
dBm
1.08
0.75
1.0954
6.02
2.1909
0
1.2
+0.2
± 0.1
1.32
+1.0
V p-p
dBm
V p-p
dBm
V
dB
dB
62.5 70
62.5
62.5 71
62.5
dB
dB
dB
dB
70
70
68
82
100
62.5
62.5
dB
dB
dB
dBm0
dB
5VEN = 0, PGA = 6 dB
5VEN = 0, PGA = 6 dB
5VEN = 0, PGA = 6 dB
5VEN = 0, PGA = 6 dB
5VEN = 0, REFOUT Unloaded
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to 50 dBm0
AVDD = +3 V ± 5%; Refer to Figure 5
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
AVDD = +3 V ± 5%
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
–2– REV. B

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AD73311
Parameter
DAC SPECIFICATIONS (Continued)
Power Supply Rejection
Group Delay4, 5
Output DC Offset2, 7
Minimum Load Resistance, RL2, 8
Single-Ended
Differential
Maximum Load Capacitance, CL2, 8
Single-Ended
Differential
FREQUENCY RESPONSE
(ADC AND DAC)9 Typical Output
0 Hz
2000 Hz
4000 Hz
8000 Hz
12000 Hz
16000 Hz
20000 Hz
24000 Hz
28000 Hz
> 32000 Hz
AD73311A
Min Typ
55
25
30 +20
150
150
Max
+70
500
100
Unit
dB
µs
mV
pF
pF
Test Conditions/Comments
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
PGA = 6 dB
0
0.1
0.25
0.6
1.4
2.8
4.5
7.0
9.5
< 12.5
dB
dB
dB
dB
dB
dB
dB Channel Frequency Response Is
dB Programmable by Means of External
dB Digital Filtering
dB
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD 0.8
0
VDD 0.4
0
10
VDD
V
0.8 V
10 µA
10 pF
VDD
V
0.4 V
+10 µA
|IOUT| 100 µA
|IOUT| 100 µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
IDD10
2.7 3.3 V
2.7 3.3 V
See Table I
NOTES
1Operating temperature range is as follows: 40°C to +85°C. Therefore, TMIN = 40°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADCs input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Between VOUTP and VOUTN.
8At VOUT output.
9Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of 10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10Test Conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = +3.3 V)
Conditions
Analog Internal Digital External Interface
Current Current
Current
ADC On Only
7
ADC and DAC On 10
REFCAP On Only 0.75
REFCAP and
REFOUT On Only 3.0
All Sections Off 0
3
5
0
0
0.85
0.5
0.5
0
0
0
All Sections Off 0.00 0.007
0
The above values are in mA and are typical values unless otherwise noted.
Total Current
(Max)
SE
11.5 1
17.5 1
1.2 0
4.5 0
1.2 0
0.04 0
MCLK
ON Comments
YES REFOUT Disabled
YES REFOUT Disabled
NO REFOUT Disabled
NO
YES MCLK Active Levels Equal to
0 V and DVDD
NO Digital Inputs Static and Equal
to 0 V or DVDD
REV. B
–3–

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AD73311–SPECIFICATIONS1 (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
FS = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
Parameter
AD73311A
Min Typ
Max
Unit Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
1.2 V 5VEN = 0
2.4 V 5VEN = 1
50 ppm/°C 0.1 µF Capacitor Required from
REFCAP to AGND2
68
1.2 V 5VEN = 0, Unloaded
2.4 V 5VEN = 1, Unloaded
2 k5VEN = 1
100 pF
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk
DC Offset
Power Supply Rejection
Group Delay4, 5
Input Resistance at VIN2, 4
3.156
3.17
2.1908
0
0.1
0.5
± 0.1
76
59
71
57
76
69
69
67
80
+20
55
25
25
V p-p
dBm
V p-p
dBm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm0
dB
mV
dB
µs
k6
5VEN = 1, Measured Differentially
5VEN = 1, Measured Differentially
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to 50 dBm0
Refer to Figure 5
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins 1.0 kHz, 100 mV p-p Sine Wave
64 kHz Output Sample Rate
DMCLK = 16.384 MHz
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single Ended
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 6 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 6 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk
3.156
3.17
6.312
9.19
2.1908
0
4.3918
6.02
VREFOUT
± 0.4
± 0.1
66
64
66
64
62.5
62.5
60
75
80
V p-p
dBm
V p-p
dBm
V p-p
dBm
V p-p
dBm
V typ
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm0
dB
5VEN = 1, PGA = 6 dB
5VEN = 1, PGA = 6 dB
5VEN = 1, PGA = 6 dB
5VEN = 1, PGA = 6 dB
5VEN = 1, REFOUT Unloaded
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to 50 dBm0
Refer to Figure 5
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
300 Hz to 3.4 kHz Frequency Range
0 Hz to 32 kHz Frequency Range
PGA = 0
PGA = 0
ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0
–4– REV. B

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AD73311
Parameter
AD73311A
Min Typ Max
Unit Test Conditions/Comments
DAC SPECIFICATIONS (Continued)
Power Supply Rejection
Group Delay4, 5
Output DC Offset2, 7
Minimum Load Resistance, RL2, 8
Single-Ended
Differential
Maximum Load Capacitance, CL2, 8
Single-Ended
Differential
55 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
25 µs 64 kHz Input Sample Rate, Interpolator
Bypassed (CRE:5 = 1)
+30 mV PGA = 6 dB
150
150
500 pF
100 pF
FREQUENCY RESPONSE
(ADC AND DAC)9 Typical Output
0 Hz
2000 Hz
4000 Hz
8000 Hz
12000 Hz
16000 Hz
20000 Hz
24000 Hz
28000 Hz
> 32000 Hz
0
0.1
0.25
0.6
1.4
2.8
4.5
7.0
9.5
< 12.5
dB
dB
dB
dB
dB
dB
dB Channel Frequency Response Is
dB Programmable by Means of External
dB Digital Filtering
dB
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD 0.8
0
0.5
10
VDD 0.4
0
0.3
VDD
0.8
VDD
0.4
V
V
µA
pF
V |IOUT| < 100 µA
V |IOUT| < 100 µA
µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
IDD10
4.5 5.5 V
4.5 5.5 V
See Table II
NOTES
1Operating temperature range is as follows: 40°C to +85°C. Therefore, TMIN = 40°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADCs input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Between VOUTP and VOUTN.
8At VOUT output.
9Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of 10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
10Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
REV. B
–5–