-ANALOGDEVICES fAX-ON-DEMAND HOTLINE
APPLYING THE ADS09
-display. The resultant waveform of (Eo EIN) of a typical
MEASURING SETTLING TIME. Settling time is defined as
that period required for an amplifier output to swing from
0 volts to full scale, usually 10 voltS, and to settle to within
a specified percentage of tbe final output voltage. For high
ADS09 is shown in Figure 3. Note that the waveform crosses
the 1mV point representing 0.01 % ac~uracy in approximately
l.S/JS. The top trace represents the output signal; the bottom
trace represents the error signal.
accuracy systems, the accuracy requirement is normally
specified as either 0.1'.16(lo-bit accuracy) or 0.01'.16(12-bit
accuracy) of the 10 volt output level. The settling time
perioo is comprised of an initial propagation delay, an
additional time for the amplifier to slew to the vicinity of
10 volts, and a final time period to'recover from internal
saturation and other effects, and settle within the specified
error band. Because settling time depends on both .linear
and nonlinear factors, there is no simple approach to
predicting itS final value to different levels of accuracy, ]n
particular, extremely high slew rates do not assure a rapid
scnling time, since this is only one of many factors affecting
settling time. In most high speed. amplifiers, after the
amplifier has slewed to the vicinity of tbe final output
voltage, it must recover from internal saturation and then
allow any overshoot and ringing to damp out. These
Odefinitions are illustrated in Figure 1.
Figure 3. Settling Time of AD509
SETTLING TIME VS. Rf AND Ri. Settling time of an
amplifier is a function of the feedback and input resistors,
since they interact with the input capacitance of the amplifier.
When operating in the non-inverting mode, the source
impedance should be kept relatively low; e.g., Sill; in order
to insure optimum performance. The small feedback
capacitor (SpF) is used in the settling time test circuit in
parallel with tbe feedback resistor to reduce ringing. This
capacitor partially cancels the pole formed in the loop gain
response as a result of the feedback and input resistors, and
the input capacitance.
SETTLING TIME VS. CAPACIT]VE LOAD. The ADS09
will drive capacitive loads of SOOpF without appreciable
deterioration in settling time. Larger capacitive loads can be
dtiven by tailoring the compensation to minimize settling
TIME SLEWING IRECOIIERYLINEAR SETTLING
time, Figure 4 shows the settling time of a typical ADS09,
compensated for unity gain witb a 1SpF capacitOr, with a
SOOpF capacitive load on the output. Note that settling time
-SETTLING TIME To1:..:lE-1
to 0.01 % is still under 2.01-15.
~:OR .:!: x100%
Figure 1. Settling Time
The AD509K and AD509S are guaranteed to settle to 0.1%
in SOOnsand 0.01" in 2.S/JS when tested as shown in Figure 2.
There is no appreciable degradation in settling time when
the capacitive load is increa.scd to 500pF, as discussed below.
The settling time is computed by summing the output and the
input into a differential amplifier, which then drives a scope
t i- f1$
Figure 4. AD509 with 500pF Capacitive Load
OMITTED fOR CLARITY
Figure 2. AD509 Settling Time Test Circuit
SUGGESTIONS FOR MINIMIZING SETTL]NG TIME. The
ADS09 has been designed to settle to 0.01 % accuracy in
1 to 2.S/JS. However, this amplifier is only a building block
in a circuit that also has a feedback network, input and output
connections, power supply connections, and a number of
external componentS. What has been painsta.kingly gained in
amplifier design can be lost without careful circuit design,
Some of the elements of a good high speed design are..........
CONNECTIONS. It is essential that care be taken in the.
signal and power ground circuits to avoid inducing or
generating extraneous voltages in the ground signal paths.