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a
FEATURES
500 MHz Driver Operation
Driver Inhibit Function
100 ps Edge Matching
Guaranteed Industry Specifications
50 Output Impedance
>1.5 V/ns Slew Rate
Variable Output Voltages for ECL, TTL and CMOS
High Speed Differential Inputs for Maximum Flexibility
Ultrasmall 20-Lead SOP Package with Built-In Heat Sink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
Ultrahigh Speed Pin Driver
with Inhibit Mode
AD53040
FUNCTIONAL BLOCK DIAGRAM
VCC VCC
VEE
VEE
VH
DATA
DATA
INH
INH
VL
DRIVER
AD53040
50
1.0A/K
39nF
39nF
VHDCPL
VOUT
VLDCPL
TVCC
THERM
GND GND GND GND GND
PRODUCT DESCRIPTION
The AD53040 is a complete high speed pin driver designed for
use in digital or mixed-signal test systems. Combining a high
speed monolithic process with a unique surface mount package,
this product attains superb electrical performance while preserv-
ing optimum packaging densities and long-term reliability in an
ultrasmall 20-lead, SOP package with built-in heat sink.
Featuring unity gain programmable output levels of –3 V to
+8 V, with output swing capability of less than 100 mV to 9 V,
the AD53040 is designed to stimulate ECL, TTL and CMOS
logic families. The 500 MHz data rate capacity and matched
output impedance allows for real-time stimulation of these
digital logic families. To test I/O devices, the pin driver can
be switched into a high impedance state (Inhibit Mode), electri-
cally removing the driver from the path. The pin driver leakage
current inhibit is typically 100 nA and output charge transfer
entering inhibit is typically less than 20 pC.
The AD53040 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high speed differential inputs with a common-mode range of
± 3 V. This allows for direct interface to precision differential
ECL timing or the simplicity of stimulating the pin driver from a
single ended TTL or CMOS logic source. The analog logic HI/LO
inputs are equally easy to interface. Typically requiring 10 µA of
bias current, the AD53040 can be directly coupled to the
output of a digital-to-analog converter.
The AD53040 is available in a 20-lead, SOP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of –25°C to +85°C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

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AD53040–SPECIFICATIONS (All specifications are at TJ = +85؇C ؎ 5؇C, +VS = +12 V ؎ 3%, –VS = –7 V ؎
3% unless otherwise noted. All temperature coefficients are measured at TJ = +75؇C–95؇C). (A 39 nF capacitor must be connected between
VCC and VHDCPL and between VEE and VLDCPL.)
Parameter
DIFFERENTIAL INPUT CHARACTERISTICS
Input Swing (Data to DATA, INH to INH)
Max (DATA, DATA) to Min (INH, INH)
Max (INH, INH) to Min (Data, DATA)
Bias Current
REFERENCE INPUTS
Bias Currents
OUTPUT CHARACTERISTICS
Logic High Range
Min
–50
–2
Logic Low Range
Amplitude (VH and VL)
Absolute Accuracy
VH Offset
VH Gain + Linearity Error
VL Offset
VL Gain + Linearity Error
Offset TC, VH or VL
Output Resistance
Output Leakage
Dynamic Current Limit
Static Current Limit
–3
0.1
–100
–100
45
–1.0
PSRR, Drive Mode
DYNAMIC PERFORMANCE, DRIVE
(VH and VL)
Propagation Delay Time
Propagation Delay TC
Delay Matching, Edge to Edge
Rise and Fall Time
1 V Swing
3 V Swing
5 V Swing
Rise and Fall Time TC
1 V Swing
3 V Swing
5 V Swing
Overshoot, Undershoot and Preshoot
Settling Time
to 15 mV
to 4 mV
Delay Change vs. Pulsewidth
Typ
ECL
± 10
± 0.3 ± 5
± 0.3 ± 5
0.5
47
150
± 65
35
Max Units
Test Conditions
2 Volts
2 Volts
µA
VIN = –2 V, 0.0 V
+50 µA
VL, VH = 5 V
+8 Volts
+5 Volts
9 Volts
DATA = H, VH = –2 V to +8 V
VL = –3 V (VH = –2 V to +6 V)
VL = –1 V (VH = +6 V to +8 V)
DATA = L, VL = –3 V to +5 V, VH = +6 V
VL = –0.05 V, VH = +0.05 V and
VL = –2 V, VH = +7 V
+100
+100
49
mV
% of VH + mV
mV
% of VL + mV
mV/°C
+1.0 µA
mA
mA
dB
DATA = H, VH = –2 V to +8 V, VL = –3 V
DATA = H, VH = –2 V to +8 V, VL = –3 V
DATA = L, VL = –3 V to +5 V, VH = +6 V
DATA = L, VL = –3 V to +5 V, VH = +6 V
VL, VH = 0 V, +5 V and –3 V, 0 V
DATA = H, VH = +3 V, VL = 0 V,
IOUT = 30 mA
VOUT = –3 V to +8 V
CBYP = 39 nF, VH = +7 V, VL = –2 V
Output to –3 V, VH = +8 V, VL = –1 V,
DATA = H and Output to +8 V, VH = +6 V,
VL = –3 V, DATA = L
VS = VS ± 3%
1.5
2
100
0.8
1.7
2.4
±1
±2
±3
± (1% +50 mV)
40
8
50
ns
ps/°C
ps
Measured at 50%, VH = +400 mV,
VL = –400 mV
Measured at 50%, VH = +400 mV,
VL = –400 mV
Measured at 50%, VH = +400 mV,
VL = –400 mV
ns Measured 20%–80%, VL = 0 V, VH = 1 V
ns Measured 10%–90%, VL = 0 V, VH = 3 V
ns Measured 10%–90%, VL = 0 V, VH = 5 V
ps/°C
ps/°C
ps/°C
% of Step + mV
Measured 20%–80%, VL = 0 V, VH = 1 V
Measured 10%–90%, VL = 0 V, VH = 3 V
Measured 10%–90%, VL = 0 V, VH = 5 V
a. VL, VH = 0.0 V, 1.0 V
b. VL, VH = 0.0 V, 3.0 V
c. VL, VH = 0.0 V, 5.0 V
ns VL = 0 V, VH = 0.5 V
µs VL = 0 V, VH = 0.5 V
ps VL = 0 V, VH = 2 V,
Pulsewidth = 2.5 ns/7.5 ns, 30 ns/100 ns
–2– REV. B

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Parameter
DYNAMIC PERFORMANCE, DRIVE
(VH and VL) (Continued)
Minimum Pulsewidth
3 V Swing
5 V Swing
Toggle Rate
Min Typ Max
Units
1.7 ns
2.6 ns
500 MHz
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
2
5 ns
Delay Time, Inhibit to Active
2 5 ns
I/O Spike
Output Capacitance
<200
5
POWER SUPPLIES
Total Supply Range
Positive Supply
Negative Supply
Positive Supply Current
Negative Supply Current
Total Power Dissipation
Temperature Sensor Gain Factor
19
+12
–7
75
75
1.15 1.43
1.0
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
Specifications subject to change without notice.
mV, p-p
pF
V
V
V
mA
mA
W
µA/K
Test Conditions
AD53040
4.0 ns Input, 10%/90% Output,
VL = 0 V, VH = 3 V
6.0 ns Input, 10%/90% Output,
VL = 0 V, VH = 5 V
VL = –1.8 V, VH = –0.8 V,
VOUT > 600 mV p-p
Measured at 50%, VH = +2 V,
VL = –2 V
Measured at 50%, VH = +2 V,
VL = –2 V
VH = 0 V, VL = 0 V
Driver Inhibited
RLOAD = 10 K, VSOURCE = +12 V
ABSOLUTE MAXIMUM RATINGS1
Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V
Inputs
DATA, DATA, INH, INH . . . . . . . . . . . . . . . . +5 V, –3 V
DATA to DATA, INH to INH . . . . . . . . . . . . . . . . . . ± 3 V
VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . +9 V, –4 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V, 0 V
Outputs
VOUT Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite2
VOUT Range in Inhibit Mode
VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC
VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V, 0 V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . . +175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . . +260°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3To ensure lead coplanarity (± 0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C
± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.
ORDERING GUIDE
Model
Package
Description
Shipment Method,
Quantity Per
Package
Shipping Container Option
AD53040KRP 20-Lead Power SOIC Tube, 38 Pieces
RP-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53040 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–

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AD53040
PIN FUNCTION DESCRIPTIONS
Pin
Name
Pin
Number Pin Functional Description
VCC 1, 2
VEE 8, 9
GND
4, 6, 14,
16, 17
VL 15
VH 18
VOUT
VHDCPL
5
3
VLDCPL
7
INH, INH 10, 11
DATA,
DATA
13, 12
TVCC
19
THERM 20
Positive Power Supply. Both pins
should be connected to minimize in-
ductance and allow maximum speed of
operation. VCC should be decoupled to
GND with a low inductance 0.1 µF
capacitor.
Negative Power Supply. Both pins
should be connected to keep the induc-
tance down and allow maximum speed
of operation. VEE should be decoupled
to GND with a low inductance 0.1 µF
capacitor.
Device Ground. These pins should be
connected to the circuit board’s ground
plane at the pins.
Analog Input that sets the voltage level
of a Logic 0 of the driver. Determines
the driver output for DATA > DATA.
Analog input that sets the voltage level
of a Logic 1 of the driver. Determines
the driver output for DATA > DATA.
The Driver Output. The nominal out-
put impedance is 50 .
Internal supply decoupling for the
output stage. This pin is connected
to VCC through a 39 nF minimum
capacitors.
Internal supply decoupling for the
output stage. This pin is connected
to VEE through a 39 nF minimum
capacitors.
ECL compatible input that control the
high impedance state of the driver.
When INH > INH, the driver goes into
a high impedance state.
ECL compatible inputs that determines
the high and low state of the driver.
Driver output is high for DATA >
DATA.
Temperature Sensor Start-Up Pin. This
pin should be connected to VCC.
Temperature Sensor Output Pin. A
resistor (10K) should be connected
between THERM and VCC. The ap-
proximate die temperature can be de-
termined by measuring the current
through the resistor. The typical scale
factor is 1 µA/K.
PIN CONFIGURATION
VCC 1
VCC 2
VHDCPL 3
GND 4
VOUT 5
GND 6
VLDCPL 7
VEE 8
VEE 9
INH 10
20 THERM
AD53040
TOP VIEW
(Not to Scale)
COPPER
SLUG UP
19 TVCC
18 VH
17 GND
16 GND
15 VL
14 GND
13 DATA
12 DATA
11 INH
DATA
0
1
0
1
Table I. Pin Driver Truth Table
DATA INH INH
1 01
0 01
1 10
0 10
Output
State
VL
VH
Hi-Z
Hi-Z
Table II. Package Thermal Characteristics
Air Flow, FM
0
50
400
JC, ؇C/W
4
4
4
JA, ؇C/W
50
49
34
–4– REV. B

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AD53040
APPLICATION INFORMATION
Power Supply Distribution, Bypassing and Sequencing
The AD53040 draws substantial transient currents from its
power supplies when switching between states and careful design
of the power distribution and bypassing is key to obtaining speci-
fied performance. Supplies should be distributed using broad,
low inductance traces or (preferably) planes in a multilayered
board with a dedicated ground-plane layer. All of the device’s
power supply pins should be used to minimize the internal in-
ductance presented by the part’s bond wires. Each supply must
be bypassed to ground with at least one 0.1 µF capacitor; chip-
style capacitors are preferable as they minimize inductance. One
or more 10 µF (or greater) Tantalum capacitors per board are
also advisable to provide additional local energy storage.
The AD53040’s current-limit circuitry also requires external
bypass capacitors. Figure 1 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in out-
put transistor Q49 creates a voltage drop across the 10 resis-
tor, which turns on PNP transistor Q48. Q48 diverts the rising-
edge slew current, shutting down the current mirror and remov-
ing the output stage’s base drive. The VHDCPL pin should be
bypassed to the positive supply with a 0.039 µF capacitor, while
the VLDCPL pin (not shown) requires a similar capacitor to the
negative supply- these capacitors ensure that the AD53040
doesn’t current limit during normal output transitions up the its
full 9 V rated step size. Both capacitors must have minimum-
length connections to the AD53040. Here again, chip capacitors
are ideal.
VPOS
10⍀؎10%
Q48
VHDCPL
RISING-EDGE SLEW
CONTROL CURRENT
LEVEL-SHIFTED
LOGIC DRIVE
VNEG
Q49
VH
Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor VBES and junction tem-
perature; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the VHDCPL
capacitor to the positive supply (and the VLDCPL capacitor to
the negative supply)—failure to do so causes considerable ther-
mal stress in the current-limiting resistor(s) during normal sup-
ply sequencing and may ultimately cause them to fail, rendering
the part nonfunctional. Finally, the AD53040 may appear to
function normally for small output steps (less than 3 V or so) if
one or both of these capacitors is absent, but it will exhibit
excessive rise or fall times for steps of larger amplitude.
The AD53040 does not require special power-supply sequencing.
However, good design practice dictates that digital and analog
control signals not be applied to the part before the supplies are
stable. Violating this guideline will not normally destroy the
part, but the active inputs can draw considerable current until
the main supplies are applied.
Digital Input Range Restrictions
Total range amongst all digital signals (DATA, DATA, INH,
and INH) has to be less than or equal to 2 V to meet specified
timing. The device will function above 2 V with reduced perfor-
mance up to the absolute maximum limit. This performance
degradation might not be noticed in all modes of operation. Of
all the six possible transitions (VH v VL, VL v VH, VH v INH,
INH v VH, VL v INH and INH v VL), there may be only one
that would show a degradation, usually in delay time. Taken to
the extreme, the driver may fail to achieve a proper output volt-
age, output impedance or may fail to fully inhibit.
An example of a scenario that would not work for the AD53040
is if the part is driven using 5 V single-ended CMOS. One pin of
each differential input would be tied to a +2.5 V reference level
and the logic voltages would be applied to the other. This would
meet the Absolute Maximum Rating of ± 3 V because the max
differential is ± 2.5 V. It is however possible, for example for
0.0 V to be applied to the INH input and +5 V to be applied to
the DATA input. This 5 V difference far exceeds the 2.0 V
limitation given above. Even using 3 V CMOS or TTL the
difference between logic high and logic low is greater than or
equal to 3 V which will not properly work. The only solution is
to use resistive dividers or equivalent to reduce the voltage levels.
OUT
Q50
Figure 1. Simplified Schematic of the AD53040 Output
Stage and Positive Current Limit Circuitry
5.12V
550mV
/DIV
REV. B
–380mV
66.25ns
500ps/DIV
71.25ns
Figure 2. 5 V Output Swing
–5–