AD402M88RPA-5.pdf 데이터시트 (총 28 페이지) - 파일 다운로드 AD402M88RPA-5 데이타시트 다운로드

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ASCEND
Semiconductor
4Mx4 EDO
Data sheet
Rev.1
Page 1

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AD 40 4M 4 2 V S A – 5
Ascend
Semiconductor
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
: 40
: 41
: 42
: 43
: 46
: 48
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Organization
4: x4
8 : x8
9 : x9
16 : x16
18 : x18
32 : x32 Refresh
1 : 1K 8 : 8K
2 : 2K 6 :16K
4 : 4K
Interface
V: 3.3V
R: 2.5V
Min Cycle Time ( Max Freq.)
-5 : 5ns ( 200MHz )
-6 : 6ns ( 167MHz )
-7 : 7ns ( 143MHz )
-75 : 7.5ns ( 133MHz )
-8 : 8ns ( 125MHz )
-10 : 10ns ( 100MHz )
EDO : -5 (50 ns)
-6 (60 ns)
Revision
A : 1st B : 2nd
C : 3rd D :4th
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
L: LQFP S: SOJ
Rev.1
Page 2

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Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-
tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).
Features
• Single 3.3V(±10 %) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
- Active mode : 432/396 mW (Mas)
- Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Rev.1
Page 3

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Pin Configuration
26/24-PIN 300mil Plastic SOJ
VCC
DQ1
DQ2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
26/24-PIN 300mil Plastic TSOP (ll)
VCC
DQ1
DQ2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin Name
Function
A0-A10
Address inputs
- Row address
- Column address
- Refresh address
A0-A10
A0-A10
A0-A10
DQ1~DQ4
Data-in / data-out
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
OE Output enable
Vcc Power (+ 3.3V)
Vss Ground
Rev.1
Page 4

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Block Diagram
WE
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
NO. 2 CLOCK
GENERATOR
COLUMN
ADDRESS
BUFFERS (11)
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFERS (11)
NO. 1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
COLUMN
DECODER
2048
SENSE AMPLIFIERS
I/O GATING
2048x4
DATA-OUT
BUFFER
2048x2048x4
MEMORY
ARRAY
DQ. 1
.
DQ4
OE
Vcc
Vss
Rev.1
Page 5