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INTEGRATED CIRCUITS
PCA9535
16-bit I2C and SMBus, low power I/O port
with interrupt
Product data
2003 Jun 27
Philips
Semiconductors

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Philips Semiconductors
16-bit I2C and SMBus, low power I/O port with interrupt
Product data
PCA9535
FEATURES
Operating power supply voltage range of 2.3 V-5.5 V
5 V tolerant I/Os
Polarity inversion register
Active LOW interrupt output
Low stand-by current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Offered in three different packages: SO24, TSSOP24, and
HVQFN24
I2C/SMBus applications and was developed to enhance the Philips
family of I2C I/O expanders. The improvements include higher drive
capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power
switches, sensors, pushbuttons, LEDs, fans, etc.
The PCA9535 consist of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active HIGH or
Active LOW operation) registers. The system master can enable the
I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding
Input or Output register. The polarity of the read register can be
inverted with the Polarity Inversion Register. All registers can be
read by the system master. Although pin-to-pin and I2C address
compatible with the PCF8575, software changes are required due to
the enhancements and are discussed in Application Note AN469.
The PCA9535 is identical to the PCA9555 except for the removal of
the internal I/O pull-up resistor which greatly reduces power
consumption when the I/Os are held LOW.
The PCA9535 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C address and
allow up to eight devices to share the same I2C/SMBus. The fixed
I2C address of the PCA9535 is the same as the PCA9554 allowing
up to eight of these devices in any combination to share the same
I2C/SMBus.
DESCRIPTION
The PCA9535 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion for
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
24-Pin Plastic SO
-40 to +85 °C
PCA9535D
PCA9535D
24-Pin Plastic TSSOP
-40 to +85 °C
PCA9535PW
PCA9535PW
24-Pin Plastic HVQFN
-40 to +85 °C
PCA9535BS
9535
Standard packing quantities and other packing data are available at www.philipslogic.com/packaging.
I2C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
DRAWING NUMBER
SOT137-1
SOT355-1
SOT616-1
2003 Jun 27
2

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Philips Semiconductors
16-bit I2C and SMBus, low power I/O port with interrupt
Product data
PCA9535
PIN CONFIGURATION — SO, TSSOP
PIN CONFIGURATION —HVQFN
INT 1
A1 2
A2 3
I/O0.0 4
I/O0.1 5
I/O0.2 6
I/O0.3 7
I/O0.4 8
I/O0.5 9
I/O0.6 10
I/O0.7 11
VSS 12
24 VDD
23 SDA
22 SCL
21 A0
20 I/O1.7
19 I/O1.6
18 I/O1.5
17 I/O1.4
16 I/O1.3
15 I/O1.2
14 I/O1.1
13 I/O1.0
SU01438
Figure 1. Pin configuration — SO, TSSOP
I/O0.0 1
I/O0.1 2
I/O0.2 3
I/O0.3 4
I/O0.4 5
I/O0.5 6
18 A0
17 I/O1.7
16 I/O1.6
15 I/O1.5
14 I/O1.4
13 I/O1.3
TOP VIEW
su01683
Figure 2. Pin configuration — HVQFN
PIN DESCRIPTION
SO,
TSSOP
PIN
NUMBER
HVQFN
PIN
NUMBER
1 22
2 23
3 24
4-1 1
1-8
12 9
13-20
10-17
21 18
22 19
23 20
24 21
SYMBOL
INT
A1
A2
I/O0.0-I/O0.7
VSS
I/O1.0-I/O1.7
A0
SCL
SDA
VDD
FUNCTION
Interrupt output (open drain)
Address input 1
Address input 2
I/O0.0 to I/O0.7
Supply ground
I/O1.0 to I/O1.7
Address input 0
Serial clock line
Serial data line
Supply voltage
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Philips Semiconductors
16-bit I2C and SMBus, low power I/O port with interrupt
Product data
PCA9535
BLOCK DIAGRAM
A0
A1
A2
SCL
SDA
VDD
VSS
INPUT
FILTER
POWER-ON
RESET
8-BIT
INPUT/
OUTPUT
PORTS
WRITE pulse
READ pulse
I/O1.0
I/O1.1
I/O1.2
I/O1.3
I/O1.4
I/O1.5
I/O1.6
I/O1.7
I2C/SMBUS
CONTROL
8-BIT
WRITE pulse
INPUT/
OUTPUT
PORTS
READ pulse
LP FILTER
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
VINT
INT
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
Figure 3. Block diagram
SU01439
2003 Jun 27
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Philips Semiconductors
16-bit I2C and SMBus, low power I/O port with interrupt
SIMPLIFIED SCHEMATIC OF I/Os
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE CONFIGURATION
PULSE
WRITE PULSE
CONFIGURATION
REGISTER
DQ
FF
CK Q
READ PULSE
DQ
FF
CK Q
OUTPUT
PORT
REGISTER
Q1
INPUT PORT
REGISTER
DQ
FF
CK Q
Q2
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
DQ
FF
CK Q
POLARITY
INVERSION
REGISTER
NOTE: At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input. The input voltage may be raised
above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either VDD or VSS.
Product data
PCA9535
OUTPUT PORT
REGISTER DATA
VDD
I/O PIN
VSS
INPUT PORT
REGISTER DATA
TO INT
POLARITY
REGISTER DATA
SU01682
2003 Jun 27
5