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March 1992
96L02 DM96L02
Dual Retriggerable Resettable
Monostable Multivibrator
General Description
The 96L02 is a dual TTL monostable multivibrator with trig-
ger mode selection reset capability rapid recovery inter-
nally compensated reference levels and high speed capabil-
ity Output pulse duration and accuracy depend on external
timing components and are therefore under user control for
each application It is well suited for a broad variety of appli-
cations including pulse delay generators square wave gen-
erators long delay timers pulse absence detectors fre-
quency detectors clock pulse generators and fixed-frequen-
cy dividers Each input is provided with a clamp diode to
limit undershoot and minimize ringing induced by fast fall
times acting on system wiring impedances
Features
Y Retriggerable 0% to 100% duty cycle
Y DC level triggering insensitive to transition times
Y Leading or trailing-edge triggering
Y Complementary outputs with active pull-ups
Y Pulse width compensation for DVCC and DTA
Y 50 ns to % output pulse width range
Y Optional retrigger lock-out capability
Y Resettable for interrupt operations
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL F 10203 – 1
Order Number 96L02DMQB
96L02FMQB or DM96L02N
See NS Package Number J16A N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
I0
I1
CD
Q
Q
CX
RX
Description
Trigger Input (Active Falling Edge)
Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
Positive Pulse Output
Complementary Pulse Output
External Capacitor Connection
External Resistor Connection
TL F 10203 – 2
C1995 National Semiconductor Corporation TL F 10203
RRD-B30M105 Printed in U S A

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Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
Military
b55 C to a125 C
Commercial
0 C to a70 C
Storage Temperature Range
b65 C to a150
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
tw (L)
tw (H)
tw (min)
tw
RX
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating
Temperature
Minimum Input Pulse
Width I1 I0
Minimum Output Pulse
Width at Q Q
Output Pulse Width Q Q
Timing Resistor Range
Conditions
VCC e 5 0V
VCC e 5 0V
RX e 20 kX
CX e 0
CL e 15 pF
VCC e 5 0V
RX e 39 kX
CX e 1000 pF
96L02 (Mil)
Min Nom Max
45 5 55
2
07
0 36
48
b55
125
50
10 300
11 5 14 2
100
DM96L02 (Com)
Min Nom Max
4 75 5 5 25
2
07
0 36
48
0 70
110
12 4 15 2
220
Units
V
V
V
mA
mA
C
ns
ns
ms
kX
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
VCC e Min II e b10 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
VCC e Min IOL e Max
VIL e Min VIL e Max
VCC e Max VI e 5 5V
24
IIH
High Level Input Current
VCC e Max VI e 2 4V
IIL
Low Level Input Current
VCC e Max VI e 0 3V
IOS
Short Circuit Output Current
VCC e Max (Note 2) VO e 1 0V
b2 0
ICC Supply Current
VCC e Max (Note 3)
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3 ICC is measured with all outputs open and all inputs grounded
Typ
(Note 1)
Max
b1 5
03
1
20
b0 4
b13 0
16
Units
V
V
V
mA
mA
mA
mA
mA
2

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Switching Characteristics VCC e a5 0V TA e a25 C
Symbol
Parameter
Conditions
tPLH
tPHL
tPLH
tPHL
Propagation Delay I0 to Q
I1 to Q
Propagation Delay I0 to Q
I1 to Q
Propagation Delay CD to Q
CD to Q
VCC e 5 0V RX e 20 kX
CX e 0 CL e 15 pF
VCC e 5 0V RX e 20 kX
CX e 0 CL e 15 pF
VCC e 5 0V RX e 39 kX
CX e 1000 pF
96L02 (Mil)
Min Max
75
62
100
Functional Block Diagram
DM96L02 (Com)
Min Max
80
65
Units
ns
ns
ns
Operation Notes
1 TRIGGERING can be accomplished by a positive-going
transition on pin 4 (12) or a negative-going transition on
pin 5 (11) Triggering begins as a signal crosses the input
VIL VIH threshold region this activates an internal latch
whose unbalanced cross-coupling causes it to assume a
preferred state As the latch output goes LOW it disables
the gates leading to the Q output and through an invert-
er turns on the capacitor discharge transistor The invert-
ed signal is also fed back to the latch input to change its
state and effectively end the triggering action thus the
latch and its associated feed-back perform the function of
a differentiator
The emitters of the latch transistors return to ground
through an enabling transistor which must be turned off
between successive triggers in order for the latch to pro-
ceed through the proper sequence when triggering is de-
sired Pin 5 (11) must be HIGH in order to trigger at pin 4
(12) conversely pin 4 (12) must be LOW in order to trig-
ger at pin 5 (11)
2 RETRIGGERING In a normal cycle triggering initiates a
rapid discharge of the external timing capacitor followed
by a ramp voltage run-up at pin 2 (14) The delay will time
out when the ramp voltage reaches the upper trigger
point of a Schmitt circuit causing the outputs to revert to
the quiescent state If another trigger occurs before the
ramp voltage reaches the Schmitt threshold the capaci-
tor will be discharged and the ramp will start again without
having disturbed the output The delay period can there-
fore be extended for an arbitrary length of time by insur-
ing that the interval between triggers is less than the de-
lay time as determined by the external capacitor and re-
sistor
3 NON-RETRIGGERABLE OPERATION Retriggering can
be inhibited logically by connecting pin 6 (10) back to pin
4 (12) or by connecting pin 7 (9) back to pin 5 (11) Either
hook-up has the effect of keeping the latch-enabling tran-
sistor turned on during the delay period which prevents
the input latch from cycling as discussed above in the
section on triggering
TL F 10203 – 3
4 OUTPUT PULSE WIDTH An external resistor RX and an
external capacitor CX are required as shown in the func-
tional block diagram To minimize stray capacitance and
noise pickup RX and CX should be located as close as
possible to the circuit In applications which require re-
mote trimming of the pulse width as with a variable resis-
tor RX should consist of a fixed resistor in series with the
variable resistor the fixed resistor should be located as
close as possible to the circuit The output pulse width tw
is defined as follows where RX is in kX CX is in pF and
tw is in ns
tw e 0 33 RXCX (1 a 3 RX) for CX t 103 pF
16 kX s RX s 220 kX for 0 C to a75 C
20 kX s RX s 100 kX for b55 C to a125 C
CX may vary from 0 to any value For pulse widths with CX
less than 103 pF see Figure a
5 SETUP AND RELEASE TIMES The setup times listed
below are necessary to allow the latch-enabling transistor
to turn off and the node voltages within the input latch to
stabilize thus insuring proper cycling of the latch when
the next trigger occurs The indicated release times
(equivalent to trigger duration) allow time for the input
latch to cycle and its signal to propagate
Input to Pin 5 (11)
Pin 4 (12) e L
Pin 3 (13) e H
TL F 10203 – 4
3

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Operation Notes (Continued)
respond to the trigger If the reset input goes HIGH coinci-
dent with a trigger transition the circuit will respond to the
trigger
96L02 Pulse Width vs RX and CX
Input to Pin 4 (12)
Pins 5 (11) and 3 (13) e H
TL F 10203 – 5
6 RESET OPERATION A LOW signal on CD pin 3 (13)
will terminate an output pulse causing Q to go LOW and
Q to go HIGH As long as CD is held LOW a delay period
cannot be initiated nor will attempted triggering cause
spikes at the outputs A reset pulse duration in the LOW
state of 25 ns is sufficient to insure resetting If the reset
input goes LOW at the same time that a trigger transition
occurs the reset will dominate and the outputs will not
Typical Characteristics
tw vs VCC
tw(min) vs TA
FIGURE a
TL F 10203 – 6
tw vs TA
TL F 10203 – 7
INPUT PULSE
f j 25 kHz
Amp j 3 0V
Width j 100 ns
tr e tf s 10 ns
FIGURE b
4
TL F 10203 – 8

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Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 96L02DMQB
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM96L02N
NS Package Number N16E
5