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October 1988
Revised March 2000
DM96LS02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
The DM96LS02 is a dual retriggerable and resettable
monostable multivibrator. The one-shot provides excep-
tionally wide delay range, pulse width stability, predictable
accuracy and immunity to noise. The pulse width is set by
an external resistor and capacitor. Resistor values up to 1.0
Mreduce required capacitor values. Hysteresis is pro-
vided on both trigger inputs of the DM96LS02 for increased
noise immunity.
Features
s Required timing capacitance reduced by factors of 10 to
100 over conventional designs
s Broad timing resistor range—1.0 kto 2.0 M
s Output Pulse Width is variable over a 2000:1 range by
resistor control
s Propagation delay of 35 ns
s 0.3V hysteresis on trigger inputs
s Output pulse width independent of duty cycle
s 35 ns to output pulse width range
Ordering Code:
Order Number Package Number
Package Description
DM96LS02M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM96LS02N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
VCC = Pin 16
GND = Pin 8
Pin Descriptions
Pin
Names
Description
I0 Trigger Input (Active Falling Edge)
I0 Schmitt Trigger Input (Active Falling Edge)
I1 Schmitt Trigger Input (Active Rising Edge)
CD Direct Clear Input (Active LOW)
Q True Pulse Output
Q Complementary Pulse Output
© 2000 Fairchild Semiconductor Corporation DS009816
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Functional Description
The DM96LS02 dual retriggerable resettable monostable
multivibrator has two DC coupled trigger inputs per func-
tion, one active LOW (I0) and one active HIGH (I1). The I1
input and I0 input of the DM96LS02 utilize an internal
Schmitt trigger with hysteresis of 0.3V to provide increased
noise immunity. The use of active HIGH and LOW inputs
allows either rising or falling edge triggering and optional
non-retriggerable operation. The inputs are DC coupled
making triggering independent of input transition times.
When input conditions for triggering are met, the Q output
goes HIGH and the external capacitor is rapidly discharged
and then allowed to recharge. An input trigger which occurs
Logic Diagram
during the timing cycle will retrigger the circuit and result in
Q remaining HIGH. The output pulse may be terminated (Q
to the LOW state) at any time by setting the Direct Clear
input LOW. Retriggering may be inhibited by tying the Q
output to I0 or the Q output to I1. Differential sensing tech-
niques are used to obtain excellent stability over tempera-
ture and power supply variations and a feedback
Darlington capacitor discharge circuit minimizes pulse
width variation from unit to unit. Schottky TTL output stages
provide high switching speeds and output compatibility with
all TTL logic families.
Operation Notes
TIMING
1. An external resistor (RX) and an external capacitor (CX)
are required as shown in the Logic Diagram. The value of
RX may vary from 1.0 kto 1.0 M.
2. The value of CX may vary from 0 to any necessary value
available. If, however, the capacitor has significant leakage
relative to VCC/RX the timing equations may not represent
the pulse width obtained.
3. The output pulse width tW for RX 10 kand CX
1000 pF is determined as follows:
tW = 0.43 RXCX
Where RX is in k, CX is in pF, t is in ns or RX is in k, CX
is in µF, t is in ms.
4. The output pulse width for RX < 10 kor CX < 1000 pF
should be determined from pulse width versus CX or RX
graphs.
5. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
TRIGGERING
1. The minimum negative pulse width into I0 is 8.0 ns; the
minimum positive pulse width into I1 is 12 ns.
2. Input signals to the DM96LS02 exhibiting slow or noisy
transitions can use either trigger as both are Schmitt trig-
gers.
3. When non-retriggerable operation is required, i.e., when
input triggers are to be ignored during quasi-stable state,
input latching is used to inhibit retriggering.
4. An overriding active LOW level direct clear is provided
on each multivibrator. By applying a LOW to the clear, any
timing cycle can be terminated or any new cycle inhibited
until the LOW reset input is removed. Trigger inputs will not
produce spikes in the output when the reset is held LOW. A
LOW-to-HIGH transition on CD will not trigger the
DM96LS02. If the CD input goes HIGH coincident with a
trigger transition, the circuit will respond to the trigger.
6. Under any operating condition, CX and RX (Min) must be
kept as close to the circuit as possible to minimize stray
capacitance and reduce noise pickup.
7. VCC and ground wiring should conform to good high fre-
quency standards so that switching transients on VCC and
ground leads do not cause interaction between one shots.
Use of a 0.01 µF to 0.1 µF bypass capacitor between VCC
and ground located near the circuit is recommended.
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Operation Notes (continued)
Triggering Truth Table
Pin Numbers
5(11)
4(12)
3(13)
HL
L
H
H LH H
XXL
H = HIGH Voltage Level VIH
L = LOW Voltage Level VIL
X = Immaterial (either H or L)
HL = HIGH-to-LOW Voltage Level Transition
LH = LOW-to-HIGH Voltage Level Transition
Operation
Trigger
Trigger
Reset
Typical Performance Characteristics
Output tW vs. RX and CX
I1 Delay Time vs. TA
I0 Delay Time vs. TA
Output tW vs. TA
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Typical Performance Characteristics (continued)
Normalized tW vs. TA
Pulse Width vs. RX CX
Input Pulse
f 100 kHz
Amp 3.0V
Width 100 ns
tr = tf 5 ns
FIGURE 1.
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Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
Min
4.75
2
Nom
5
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max
Input Voltage
IIH HIGH Level Input Current
IIL LOW Level Input Current
IOS Short Circuit Output Current
ICC Supply Current
VT+ Positive-Going Threshold
Voltage, I0, I1
VCC = Min, II = −18 mA
VCC = Min, IOH = Max,
VIL = Max
VCC = Min, IOL = Max,
VIH = Min
IOL = 4 mA, VCC = Min
VCC = Max, VI = 7V
VI = 10V
VCC = Max, VI = 2.7V
VCC = Max, VI = 0.4V
VCC = Max (Note 3)
VCC = Max
2.7
20
VTNegative-Going Threshold
Voltage, I0, I1
0.8
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Max
Units
5.25
V
V
0.8 V
0.4
mA
8 mA
70 °C
Typ
(Note 2)
3.4
Max
1.5
0.35 0.5
0.25 0.4
0.1
20
0.4
100
36
2.0
Units
V
V
V
mA
µA
mA
mA
mA
V
V
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