Circuit Description and Application Notes: continued
Current Limit Limit
The output stage is protected against short circuit condi-
tions. As shown in Figure 2, the output current will fold
back when the faulted load is continually increased. This
technique has been incorporated to limit the total power
dissipation across the device during a short circuit condi-
tion, since the device does not contain overtemperature
* Curve will vary with temperature and process variation.
0.00 0.51 1.02 1.52 2.03 2.54 3.05 3.56 4.06 4.57 5.08
Figure 2. Typical current limit and fold back waveform.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
* CIN required if regulator is located far from the power supply filter.
** COUT required for stability. Capacitor must operate at minimum
*** Pin internally shorted to VOUT in 3 pin applications.
Figure 3: Test and application circuit showing output compensation.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabil-
ity. The aluminum electrolytic capacitor is the least expen-
sive solution, but, if the circuit operates at low tempera-
tures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufac-
turers data sheet usually provides this information.
The value for the output capacitor COUT shown in Figure 3
should work for most applications, however it is not nec-
essarily the best solution.
To determine an acceptable value for COUT for a particular
application, start with a tantalum capacitor of the recom-
mended value and work towards a less expensive alterna-
Step 1: Place the completed circuit with a tantalum capac-
itor of the recommended value in an environmental cham-
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by
the longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage condi-
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capaci-
tor will usually cost less and occupy less board space. If
the output oscillates within the range of expected operat-
ing conditions, repeat steps 3 and 4 with the next larger
standard capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regula-
tor performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low tem-
peratures. The ESR of the capacitor should be less than 50%
of the maximum allowable ESR found in step 3 above.