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CS8420
Digital Audio Sample Rate Converter
Features
General Description
 Complete IEC60958, AES3, S/PDIF, EIAJ
CP1201-compatible Transceiver with
Asynchronous Sample Rate Converter
 Flexible 3-wire Serial Digital I/O Ports
 8-kHz to 108-kHz Sample Rate Range
www.DataSheet4U.com
 1:3 and 3:1 Maximum Input to Output Sample
Rate Ratio
 128 dB Dynamic Range
 -117 dB THD+N at 1 kHz
 Excellent Performance at Almost a 1:1 Ratio
 Excellent Clock Jitter Rejection
 24-bit I/O Words
 Pin and Microcontroller Read/Write Access to
Channel Status and User Data
 Microcontroller and Stand-Alone Modes
The CS8420 is a stereo digital audio sample rate con-
verter (SRC) with AES3-type and serial digital audio
inputs, AES3-type and serial digital audio outputs, and
includes comprehensive control ability via a 4-wire mi-
crocontroller port. Channel status and user data can be
assembled in block-sized buffers, making
read/modify/write cycles easy.
Digital audio inputs and outputs may be 24, 20, or 16
bits. The input data can be completely asynchronous to
the output data, with the output data being synchronous
to an external system clock.
The CS8420 is available in a 28-pin SOIC package in
both Commercial (-10º to +70º C) and Automotive
grades (-40º to +85º C). The CDB8420 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions.
Please refer to “Ordering Information” on page 93 for or-
dering information.
Target applications include CD-R, DAT, MD, DVD and
VTR equipment, mixing consoles, digital audio trans-
mission equipment, high-quality D/A and A/D
converters, effects processors, and computer audio
systems.
VA+ AGND FILT RERR RMCK
VD+ DGND
ILRCK
ISCLK
SDIN
RXP
RXN
Serial
Audio
Input
Sample
Rate
Converter
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
Receiver
Clock & AES3
Data
S/PDIF
Recovery Decoder
C & U bit
Data
Buffer
AES3
S/PDIF
Encoder
Driver
TXP
TXN
Misc.
Control
Control
Port &
Registers
Output
Clock
Generator
H/S RST
EMPH U TCBL SDA/ SCL/ AD1/ AD0/ INT
CDOUT CCLK CDIN CS
OMCK
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
APRIL '07
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CS8420
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
SPECIFIED OPERATING CONDITIONS .............................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
PERFORMANCE SPECIFICATIONS .................................................................................................... 7
DIGITAL FILTER CHARACTERISTICS ................................................................................................. 7
DC ELECTRICAL SPECIFICATIONS .................................................................................................... 7
DIGITAL INPUT CHARACTERISTICS .................................................................................................. 8
DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 8
TRANSMITTER CHARACTERISTICS .................................................................................................. 8
SWITCHING CHARACTERISTICS ....................................................................................................... 8
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS .............................................................. 9
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE ............................................. 10
www.DataSheet4U.com SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE ............................................... 11
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12
3. GENERAL DESCRIPTION ................................................................................................................... 13
4. DATA I/O FLOW AND CLOCKING OPTIONS ..................................................................................... 14
5. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 18
5.1 Dither ............................................................................................................................................. 18
5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register ..................................................... 18
6. THREE-WIRE SERIAL AUDIO PORTS ............................................................................................... 19
7. AES3 TRANSMITTER AND RECEIVER .............................................................................................. 22
7.1 AES3 Receiver ............................................................................................................................... 22
7.1.1 PLL, Jitter Attenuation, and Varispeed .................................................................................. 22
7.1.2 OMCK Out On RMCK ........................................................................................................... 22
7.1.3 Error Reporting and Hold Function ........................................................................................ 22
7.1.4 Channel Status Data Handling .............................................................................................. 23
7.1.5 User Data Handling ............................................................................................................... 23
7.1.6 Non-Audio Auto Detection ..................................................................................................... 24
7.2 AES3 Transmitter ........................................................................................................................... 24
7.2.1 Transmitted Frame and Channel Status Boundary Timing ................................................... 24
7.2.2 TXN and TXP Drivers ............................................................................................................ 25
7.3 Mono Mode Operation ................................................................................................................... 25
8. AES3 TRANSMITTER AND RECEIVER .............................................................................................. 28
8.1 Sample Rate Converter ................................................................................................................. 28
8.2 Non-SRC Delay ............................................................................................................................. 29
9. CONTROL PORT DESCRIPTION AND TIMING ................................................................................. 30
9.1 SPI Mode ....................................................................................................................................... 30
9.2 I²C Mode ........................................................................................................................................ 31
9.3 Interrupts ........................................................................................................................................ 31
10. CONTROL PORT REGISTER BIT DEFINITIONS ............................................................................. 32
10.1 Memory Address Pointer (MAP) .................................................................................................. 32
10.2 Miscellaneous Control 1 (01h) ..................................................................................................... 34
10.3 Miscellaneous Control 2 (02h) ..................................................................................................... 35
10.4 Data Flow Control (03h) ............................................................................................................... 36
10.5 Clock Source Control (04h) .......................................................................................................... 37
10.6 Serial Audio Input Port Data Format (05h) ................................................................................... 38
10.7 Serial Audio Output Port Data Format (06h) ................................................................................ 39
10.8 Interrupt 1 Register Status (07h) (Read Only) ............................................................................. 40
10.9 Interrupt Register 2 Status (08h) (Read Only) ............................................................................. 41
10.10 Interrupt 1 Register Mask (09h) ................................................................................................. 41
10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh) ..................................................... 41
10.12 Interrupt 2 Register Mask (0Ch) ................................................................................................. 42
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10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) ..................................................... 42
10.14 Receiver Channel Status (0Fh) (Read Only) ............................................................................. 43
10.15 Receiver Error (10h) (Read Only) .............................................................................................. 44
10.16 Receiver Error Mask (11h) ......................................................................................................... 45
10.17 Channel Status Data Buffer Control (12h) ................................................................................. 45
10.18 User Data Buffer Control (13h) .................................................................................................. 46
10.19 Sample Rate Ratio (1Eh) (Read Only) ....................................................................................... 47
10.20 C-Bit or U-Bit Data Buffer (20h - 37h) ........................................................................................ 47
10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ............................................................... 47
11. SYSTEM AND APPLICATIONS ISSUES ........................................................................................... 48
11.1 Reset, Power Down and Start-up Options ................................................................................... 48
11.2 Transmitter Startup ...................................................................................................................... 48
11.3 SRC Invalid State ......................................................................................................................... 49
www.DataSheet4U.com 11.4 C/U Buffer Data Corruption .......................................................................................................... 49
11.5 Block-Mode U-Data D-to-E Buffer Transfers ............................................................................... 50
11.6 ID Code and Revision Code ........................................................................................................ 50
11.7 Power Supply, Grounding, and PCB layout ................................................................................. 50
11.8 Synchronization of Multiple CS8420s .......................................................................................... 50
11.9 Extended Range Sample Rate Conversion ................................................................................. 50
12. SOFTWARE MODE - PIN DESCRIPTION ......................................................................................... 51
13. HARDWARE MODES ......................................................................................................................... 55
13.1 Overall Description ....................................................................................................................... 55
13.1.1 Hardware Mode Definitions ................................................................................................. 55
13.1.2 Serial Audio Port Formats ................................................................................................... 55
13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) ............................................ 56
13.2.1 Pin Description - Hardware Mode 1 .................................................................................... 57
13.3 Hardware Mode 2 Description ..................................................................................................... 59
13.3.1 Pin Description - Hardware Mode 2 .................................................................................... 61
13.4 Hardware Mode 3 Description ..................................................................................................... 63
13.4.1 Pin Description - Hardware Mode 3 .................................................................................... 65
13.5 Hardware Mode 4 Description ..................................................................................................... 67
13.5.1 Pin Description - Hardware Mode 4 .................................................................................... 69
13.6 Hardware Mode 5 Description ..................................................................................................... 71
13.6.1 Pin Description - Hardware Mode 5 .................................................................................... 72
13.7 Hardware Mode 6 Description ..................................................................................................... 74
13.7.1 Pin Description - Hardware Mode 6 .................................................................................... 76
14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS ................ 78
14.1 AES3 Transmitter External Components ..................................................................................... 78
14.2 AES3 Receiver External Components ......................................................................................... 79
14.3 Isolating Transformer Requirements ............................................................................................ 80
15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT .................................................. 81
15.1 AES3 Channel Status(C) Bit Management .................................................................................. 81
15.1.1 Manually Accessing the E Buffer ......................................................................................... 82
15.1.2 Reserving the First 5 Bytes in the E Buffer ......................................................................... 83
15.1.3 Serial Copy Management System (SCMS) ......................................................................... 83
15.1.4 Channel Status Data E Buffer Access ................................................................................. 83
15.1.5 One-Byte Mode ................................................................................................................... 84
15.1.6 Two-Byte Mode ................................................................................................................... 84
15.2 AES3 User (U) Bit Management .................................................................................................. 84
15.2.1 Mode 1: Transmit All Zeros ................................................................................................. 84
15.2.2 Mode 2: Block Mode ............................................................................................................ 84
15.2.3 IEC60958 Recommended U Data Format for Consumer Applications ............................... 85
15.2.4 Mode (3): Reserved ............................................................................................................. 85
15.2.5 Mode (4): IEC Consumer B ................................................................................................. 85
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16. PLL FILTER ........................................................................................................................................ 87
16.1 General ........................................................................................................................................ 87
16.2 External Filter Components ......................................................................................................... 87
16.2.1 General ................................................................................................................................ 87
16.2.2 Capacitor Selection ............................................................................................................. 88
16.2.3 Circuit Board Layout ............................................................................................................ 88
16.3 Component Value Selection ........................................................................................................ 88
16.3.1 Identifying the Part Revision ................................................................................................ 88
16.3.2 Locking to the RXP/RXN Receiver Inputs ........................................................................... 89
16.3.3 Locking to the ILRCK Input ................................................................................................. 89
16.3.4 Jitter Tolerance .................................................................................................................... 90
16.3.5 Jitter Attenuation ................................................................................................................. 90
17. PARAMETER DEFINITIONS .............................................................................................................. 91
www.DataSheet4U.com 18. PACKAGE DIMENSIONS .................................................................................................................. 92
THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................................. 92
19. ORDERING INFORMATION .............................................................................................................. 93
20. REVISION HISTORY .......................................................................................................................... 93
LIST OF FIGURES
Figure 1.Audio Port Master Mode Timing ................................................................................................... 9
Figure 2.Audio Port Slave Mode and Data Input Timing ............................................................................. 9
Figure 3.SPI Mode Timing ........................................................................................................................ 10
Figure 4.I²C Mode Timing ......................................................................................................................... 11
Figure 5.Recommended Connection Diagram for Software Mode ........................................................... 12
Figure 6.Software Mode Audio Data Flow Switching Options ................................................................... 14
Figure 7.CS8420 Clock Routing ................................................................................................................ 14
Figure 8.Serial Audio Input, using PLL, SRC Enabled .............................................................................. 16
Figure 9.Serial Audio Input, No PLL, SRC Enabled .................................................................................. 16
Figure 10.AES3 Input, SRC Enabled ........................................................................................................ 16
Figure 11.Serial Audio Input, AES3 Input Clock Source, SRC Enabled ................................................... 16
Figure 12.Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock ....................................... 16
Figure 13.AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out ............................... 16
Figure 14.AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC ......................... 17
Figure 15.AES3 Input to Serial Audio Output Only ................................................................................... 17
Figure 16.Input Serial Port to AES3 Transmitter ....................................................................................... 17
Figure 17.Serial Audio Input Example Formats ........................................................................................ 20
Figure 18.Serial Audio Output Example Formats ...................................................................................... 21
Figure 19.AES3 Receiver Timing for C & U Pin Output Data ................................................................... 23
Figure 20.AES3 Transmitter Timing for C, U and V Pin Input Data .......................................................... 26
Figure 21.Mono Mode Operation Compared to Normal Stereo Operation ............................................... 27
Figure 22.Control Port Timing in SPI Mode .............................................................................................. 30
Figure 23.Control Port Timing in I²C Mode ............................................................................................... 31
Figure 24.Hardware Mode 1 - Default Data Flow, AES3 Input ................................................................. 56
Figure 25.Hardware Mode 2 - Default Data Flow, Serial Audio Input ....................................................... 59
Figure 26.Hardware Mode 3 - Transceive Data Flow, with SRC .............................................................. 63
Figure 27.Hardware Mode 4 - Transceive Data Flow, Without SRC ......................................................... 67
Figure 28.Hardware Mode 5 - AES3 Receiver Only ................................................................................. 71
Figure 29.Hardware Mode 6 - AES3 Transmitter Only ............................................................................. 74
Figure 30.Professional Output Circuit ....................................................................................................... 78
Figure 31.Consumer Output Circuit .......................................................................................................... 78
Figure 32.TTL/CMOS Output Circuit ......................................................................................................... 79
Figure 33.Professional Input Circuit .......................................................................................................... 79
Figure 34.Transformerless Professional Input Circuit ............................................................................... 79
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Figure 35.Consumer Input Circuit ............................................................................................................. 80
Figure 36.TTL/CMOS Input Circuit ............................................................................................................ 80
Figure 37.Channel Status Data Buffer Structure ....................................................................................... 81
Figure 38.Channel Status Block Handling When Fso is Not Equal to Fsi ................................................. 82
Figure 39.Flowchart for Reading the E Buffer ........................................................................................... 82
Figure 40.Flowchart for Writing the E Buffer ............................................................................................. 83
Figure 41.PLL Block Diagram ................................................................................................................... 87
Figure 42.Recommended Layout Example ............................................................................................... 88
Figure 43.Jitter Tolerance Template ......................................................................................................... 90
Figure 44.Revision D Jitter Attenuation ..................................................................................................... 90
Figure 45.Revision D1 Jitter Attenuation ................................................................................................... 90
LIST OF TABLES
www.DataSheet4U.com Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN ...................... 28
Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK ........................... 28
Table 3. Non-SRC Delay ........................................................................................................................... 29
Table 4. Summary of all Bits in the Control Register Map ........................................................................ 33
Table 5. Hardware Mode Definitions ......................................................................................................... 55
Table 6. Serial Audio Output Formats Available in Hardware Mode ......................................................... 55
Table 7. Serial Audio Input Formats Available in Hardware Mode ............................................................ 55
Table 8. Hardware Mode 1 Start-Up Options ............................................................................................ 56
Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function ...................................................................... 60
Table 10. HW Mode 2 Serial Audio Port Format Selection ....................................................................... 60
Table 11. Hardware Mode 2 Start-Up Options .......................................................................................... 60
Table 12. Hardware Mode 3 Start-Up Options .......................................................................................... 64
Table 13. Hardware Mode 4 Start-Up Options .......................................................................................... 68
Table 14. Hardware Mode 5 Start-Up Options .......................................................................................... 71
Table 15. HW 6 COPY/C and ORIG Pin Function .................................................................................... 75
Table 16. HW 6 Serial Port Format Selection ........................................................................................... 75
Table 17. Second Line Part Marking ......................................................................................................... 88
Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz ................................................................................... 89
Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* ................................................................................ 89
Table 20. Locking to the ILRCK Input ....................................................................................................... 89
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