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October 2000
Revision 2.1
Geode™ CS9211 Graphics Companion
Flat Panel Display Controller
General Description
The National Semiconductor® Geode™ CS9211 graphics
companion is suitable for systems that use any GX-series
processor (e.g., GX1, GXLV, GXm) along with the
CS5530A I/O companion, also members of the Geode fam-
ily of products.
The CS9211 converts the digital pixel stream output of the
CS5530A to the digital RGB inputs used by standard single
and dual-scan STN LCD display panels. Support is pro-
vided for both color and monochrome dual-scan STN
(DSTN) flat panels up to 1024x768 resolution, and for color
single-scan panels up to 640x480 resolution.
The typical system connection shows how to connect the
CS9211 with other system components. Note that the
external frame buffer is only required for DSTN panels.
Features
s Supports most SVGA DSTN panels and the VESA FPDI
(Flat Panel Display Interface) Revision 1.0 Specification.
s Directly interfaces to panels; no external drivers needed
(excluding backlight inverter).
s Supports 18-bit color pixel input data stream in 6:6:6
format, for a maximum display of 262,144 colors.
s Supports up to 65 MHz pixel clock (DOTCLK).
s Supports resolutions up to 1024x768 pixels.
s Fast display refresh rate, up to 120 Hz for DSTN panels,
achieved by writing both panel halves simultaneously.
s 16- or 24-bit dual-scan color STN (DSTN) support.
s 8- or 16-bit dual-scan monochrome STN (DSTN)
support.
s 8-bit single-scan color STN (SSTN) panel support.
s TFT panel support provided via pass-through mode.
s 9-, 12- or 18-bit TFT support.
s 9+9 or 12+12-bit, 2 pixels per clock TFT panel support.
s Frame rate modulation (FRM) allows up to 32 shades of
gray (intensities) for each primary color (R,G,B) with no
loss of spatial resolution.
s Proprietary dithering algorithm allows display of addi-
tional colors for a maximum of 262,144 colors.
s Programmable control of input and output sync pulse
widths, delays, and polarities allows interfaces to many
panel types.
s Programmable panel power sequence controls.
s Built-in memory controller supports either SDRAM or
EDO memory for the DSTN frame buffer.
s Configuration via a serial programming interface.
s Low-power, 3.3V operation.
s 144-pin LQFP (Low-profile Quad Flat Pack).
Typical System Connection
Pixel Data
18
Geode™
GX-Series
Processor
Geode™
CS5530A
I/O Companion
Pixel Port
18
Timing Control
4
Serial Configuration 4
Geode™
CS9211
Graphics
Companion
Panel Data
24
Panel Timing 4 LCD Panel
(TFT, DSTN,
Power Control 3
or SSTN)
Video Port (YUV) 8
16
Data
21
Address & Control
DRAM/SDRAM
(External Frame Buffer)
National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode is a trademark of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
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Table of Contents
1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
Pixel Port Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flat Panel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset, Crystal, and GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
National Semiconductor Internal Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 SYSTEM INTERCONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1
3.1.2
3.1.3
3.1.4
CS550A Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Panel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Crystal Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1.1 Write Transfer Sequence (52 clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1.2 Read Transfer Sequence (56 clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2.1 TFT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2.2 STN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2.3 Output Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.3.1 Input Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.3.2 Output Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frame Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.4.1 Removal of Flickering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FRM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6.1 Theory Of Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6.2 Pre-Programmed Dither Patterns (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6.3 Controlling Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
User-defined Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CRC Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Simultaneous Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Maximum Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.12.1 External Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.12.2 Internal Power Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.0 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Table of Contents (Continued)
5.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1 TEST MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1.1 NAND Tree Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.5 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Pixel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Flat Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Panel Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.0 Mechanical Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.1 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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1.0 Architecture Overview
The major functional blocks, as shown in Figure 1-1, of the
CS9211 graphics companion flat panel display controller:
Serial Interface
Dither Engine
Frame Rate Modulator (FRM)
Control Registers
DSTN Timing Generator
Panel Interface
Frame Accelerator
CRC (Cyclical Redundancy Check) Engine
SDRAM/DRAM Interface Controller
Serial
Configuration
4
Serial Interface
Control Registers
24 CRC
Engine
Pixel
Data
18
Dither
Engine
18
Pixel
Control
4
DSTN Timing
Generator
Frame Rate
Modulator
6
18
Frame
Accelerator
6
24 Panel
Data
Panel
Interface
7 Panel
Control
SDRAM/DRAM
Interface Controller
37
SDRAM/DRAM
Figure 1-1. Internal Block Diagram
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2.0 Signal Definitions
This section defines the signals and external interface of
the CS9211. Figure 2-1 shows the pins organized by their
functional groupings (internal test and electrical pins are
not shown).
2.1 PIN ASSIGNMENTS
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 shows the pin assignment for the CS9211 with
Tables 2-2 and 2-3 listing the pin assignments sorted by pin
number and alphabetically by signal name, respectively.
In Section 2.2 "Signal Descriptions" on page 9 a descrip-
tion of each signal within its associated functional group is
provided.
Table 2-1. Pin Type Definitions
Mnemonic
Definition
I
I/O
O
OD
PU
PD
smt
t/s
VDD (PWR)
VSS (GND)
#
Standard input pin
Bidirectional pin
Totem-pole output
Open-drain output structure that allows
multiple devices to share the pin in a
wired-OR configuration
Pull-up resistor
Pull-down resistor
Schmitt Trigger
TRI-STATE signal
Power pin
Ground pin
The "#" symbol at the end of a signal
name indicates that the active, or
asserted state occurs when the signal
is at a low voltage level. When "#" is
not present after the signal name, the
signal is asserted when at the a high
voltage level.
Pixel Port
Interface
Serial
Interface
Flat Panel
Interface
RED[5:0]
GREEN[5:0]
BLUE[5:0]
ENA_DISP
ENA_VDDIN
ENA_LCDIN
DOTCLK
FP_HSYNC
FP_VSYNC
SCLK
SDIN
SCS
SDO
LDE
LP/HSYNC
SHFCLK
FLM/VSYNC
UD[11:0]
LD[11:0]
DISPOFF#
FP_VDDEN
FP_VCONEN
Geode™
CS9211
Graphics
Companion
MA[10:0]
MD[15:0]
DQMH
DQML
OE#/BA
WE#
CASH#
CAS#/CASL#
RAS#
MCLK
CKE
CS#
Memory
Interface
RESET#
XTALIN
XTALOUT
GPIO0-GPIO7
Reset,
Crystal,
and
GPIOs
Figure 2-1. Signal Groups
Revision 2.1
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