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FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full Speed Correlated Double Sampler (CDS)
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS: 185 mW
48-Terminal TQFP Package
CCD Signal Processor
For Electronic Cameras
AD9802
FUNCTIONAL BLOCK DIAGRAM
PBLK CLPDM PGACONT1 PGACONT2 SHP SHD ADCCLK
PIN
DIN
ADCIN
CLAMP
TIMING
GENERATOR
CDS
PGA
MUX S/H
10
A/D
DOUT
REFERENCE
CLAMP
AD9802
DRVDD
DVDD
CMLEVEL VRT VRB STBY CLPOB ADCMODE ACVDD ADVDD
PRODUCT DESCRIPTION
The AD9802 is a complete CCD signal processor developed
for electronic cameras. It is suitable for both camcorder and
consumer-level still camera applications.
The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping cir-
cuitry and an onboard voltage reference are provided as well as a
direct ADC input. The AD9802 operates from a single +3 V
supply with a typical power consumption of 185 mW.
The AD9802 is packaged in a space saving 48-terminal thin
quad flatpack (TQFP) and is specified over an operating tem-
perature range of 0°C to +70°C.
PRODUCT HIGHLIGHTS
1. On-Chip Input Clamp and CDS
Clamp circuitry and high speed correlated double sampler
allow for simple ac-coupling to interface a CCD sensor at full
18 MSPS conversion rate.
2. On-Chip PGA
The AD9802 includes a low-noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).
3. Direct ADC Input
A direct input to the 10-bit A/D converter is provided for
digitizing video signals.
4. 10-Bit, High Speed A/D Converter
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. Typical DNL is ± 0.5 LSB
and no missing code performance is guaranteed.
5. Low Power
At 185 mW, and 15 mW in power-down, the AD9802 con-
sumes a fraction of the power of presently available multichip
solutions.
6. Digital I/O Functionality
The AD9802 offers three-state digital output control.
7. Small Package
Packaged in a 48-terminal, surface-mount thin quad flatpack,
the AD9802 is well suited to very compact, low headroom
designs.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997

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AD9802–SPECIFICATIONS (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V
unless otherwise noted)
Parameter
Min Typ Max
Units
TEMPERATURE RANGE
Operating
Storage
0 70 °C
–65 150 °C
POWER SUPPLY VOLTAGE (For Functional Operation)
ACVDD
ADVDD
DVDD
DRVDD
3.00 3.15 3.50 V
3.00 3.15 3.50 V
3.00 3.15 3.50 V
3.00 3.15 3.50 V
POWER SUPPLY CURRENT
ACVDD
ADVDD
DVDD
DRVDD
39.5 mA
14.6 mA
4.7 mA
0.07 mA
POWER CONSUMPTION
Normal Operation
Power-Down Mode
185 mW
15 mW
MAXIMUM SHP, SHD, ADCCLK RATE
18
MHz
ADC
Resolution
Differential Nonlinearity
No Missing Codes
ADCCLK Rate
Reference Top Voltage
Reference Bottom Voltage
Input Range
10
± 0.5
GUARANTEED
18
1.75
1.25
1.0
Bits
LSBs
MHz
V
V
V p-p
CDS
Maximum Input Signal
Pixel Rate
PGA1
Maximum Gain
High Gain
Medium Gain
Minimum Gain
500 mV p-p
18 MHz
31.5 dB
14.5 19
23.5 dB
1.0 4.0 7.0 dB
–4.0 0
+4 dB
CLAMP (During CLPOB. Only Stable over PGA Range 0.3 V to 2.7 V)
Average Black Level
Pixel-to-Pixel Offset (See Black Level Clamping for Description)
32
28
LSBs
LSBs
NOTES
1PGA test conditions: maximum gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 =
0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise
noted)
Parameter
Symbol
Min Typ Max
Units
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.4
10
10
10
0.6
V
V
µA
µA
pF
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
VOH
VOL
IOH
IOL
2.4
50
50
0.6
V
V
µA
µA
–2– REV. 0

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AD9802
TIMING SPECIFICATIONS (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise
noted)
Parameter
Min Typ Max
Units
ADCCLK Clock Period
ADCCLK Hi-Level Period
ADCCLK Lo-Level Period
SHP, SHD Clock Period
SHP, SHD Minimum Pulse Width
SHP Rising Edge to SHD Rising Edge
Digital Output Delay
55.6
24.8 27.8
24.8 27.8
55.6
12.5
28
20
ns
ns
ns
ns
ns
ns
ns
PBLK
0
1
1
1
1
Digital Output Data Control
MODE1
0
0
0
1
1
MODE2
0
0
1
0
1
Digital Output Data (D9–D0)
0000000000
Normal Operation
1010101010
0101010101
High Impedance
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect To
Min
Max
Units
ADVDD
ACVDD
DVDD
DRVDD
SHP, SHD
ADCCLK, CLPOB, CLPDM
PGACONT1, PGACONT2
PIN, DIN
DOUT
VRT, VRB
CLAMP_BIAS
CCDBYP1, CCDBYP2
STBY
MODE1, MODE2
DRVSS, DVSS, ACVSS, ADVSS
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ADVSS, SUBST
ACVSS, SUBST
DVSS, DSUBT
DRVSS, DSUBST
DSUBST
DSUBST
SUBST
SUBST
DSUBST
SUBST
SUBST
SUBST
DSUBST
SUBST
SUBST, DSUBST
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
6.5
6.5
6.5
6.5
DVDD + 2.0
DVDD + 0.3
ACVDD + 0.3
ACVDD + 0.3
DRVDD + 0.3
ADVDD + 0.3
ACVDD + 0.3
ACVDD + 0.3
DVDD + 0.3
ADVDD + 0.3
+0.3
+150
+150
+300
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
ORDERING GUIDE
Model
AD9802JST
Temperature Range
0°C to +70°C
Package Description
48-Terminal Plastic Thin Quad Flatpack
Package Option
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9802 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–

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AD9802
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
ADVSS 1
(LSB) D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
(MSB) D9 11
DRVDD 12
PIN 1
IDENTIFIER
AD9802
TOP VIEW
(Not to Scale)
36 ADCIN
35 TEST2
34 TEST1
33 ACVDD
32 CLAMP_BIAS
31 ACVSS
30 PGACONT2
29 PGACONT1
28 CCDBYP1
27 PIN
26 DIN
25 CCDBYP2
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin # Pin Name
Type
Description
1
2–11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34, 35
36
37
38
39
40
41
42
43
44, 45
46
47
48
ADVSS
D0–D9
DRVDD
DRVSS
DSUBST
DVSS
ADCCLK
DVDD
STBY
PBLK
CLPOB
SHP
SHD
CLPDM
DVSS
CCDBYP2
DIN
PIN
CCDBYP1
PGACONT1
PGACONT2
ACVSS
CLAMP_BIAS
ACVDD
TEST1, TEST2
ADCIN
CMLEVEL
SHABYP
MODE2
MODE1
ADCMODE
NC
ADVDD
ADVSS
SUBST
VRB
VRT
P
DO
P
P
P
P
DI
P
DI
DI
DI
DI
DI
DI
P
AO
AI
AI
AO
AI
AI
P
AO
P
AI
AI
AO
AO
DI
DI
DI
P
P
P
AO
AO
Analog Ground
Digital Data Outputs: D0 = LSB, D9 = MSB
+3 V Digital Driver Supply
Digital Driver Ground
Digital Substrate
Digital Ground
ADC Sample Clock Input
+3 V Digital Supply
Power-Down (Active High)
Pixel Blanking (Active Low)
Black Level Restore Clamp (Active Low)
Reference Sample Clock Input
Data Sample Clock Input
Input Clamp (Active Low)
Digital Ground
CCD Bypass. Decouple to analog ground through 0.1 µF.
CDS Input. Tie to Pin 27 and AC-Couple to CCD output through 0.1 µF.
CDS Input. See above.
CCD Bypass. Decouple to analog ground through 0.1 µF.
Coarse PGA Gain Control (0.3 V–2.7 V). Decoupled to analog ground through 0.1 µF.
Fine PGA Gain Control
Analog Ground
Clamp Bias Level. Decouple to analog ground through 0.1 µF.
+3 V Analog Supply
Reserved Test Pins. Should be left NC or pulled high to ACVDD.
Direct ADC Analog Input (See Driving the Direct ADC Input)
Common-Mode Level. Decouple to analog ground through 0.1 µF.
Internal Bias Level. Decouple to analog ground through 0.1 µF.
ADC Test Mode Control (See Digital Output Data Control.)
ADC Test Mode Control (See Digital Output Data Control.)
ADC Input Control. Logic low for CDS/PGA, high for direct input.
No Connect
+3 V Analog Supply
Analog Ground
Substrate. Connect to analog ground.
Bottom Reference Bypass. Decouple to analog ground through 0.1 µF.
Top Reference Bypass
NOTE
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
–4– REV. 0

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EQUIVALENT INPUT CIRCUITS
DVDD
DRVDD
DVSS
DRVSS
Figure 1. Pins 2–11 (DB0–DB9)
DVDD
200
DSUBST
DVSS
Figure 2. Pin 21 (SHP) and Pin 22 (SHD)
DVDD
200
DSUBST
DVSS
Figure 3. Pin 16 (ADCCLK)
ADVDD
9.3k
ADVSS
Figure 4. Pin 37 (CMLEVEL)
ACVDD
50
SUBST
ACVSS
Figure 5. Pin 25 (CCDBYP2) and Pin 28 (CCDBYP1)
AD9802
ACVDD
50
10pF
SUBST
ACVSS
Figure 6. Pin 26 (DIN) and Pin 27 (PIN)
ACVDD
PGACONT1
PGACONT2
SUBST
ACVDD
8k
10k
1k
8k
Figure 7. Pin 29 (PGACONT1) and Pin 30 (PGACONT2)
ACVDD
200
SUBST
10k
30k
ACVSS
Figure 8. Pin 32 (CLAMP BIAS)
3k
ADVDD
1.1k
200
SUBST
ADVSS
Figure 9. Pin 48 (VRT) and Pin 47 (VRB)
ACVDD
50
SUBST
1pF
Figure 10. Pin 36 (ADCIN) and Pin 38 (SHABYP)
REV. 0
–5–