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a
FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB ؎ 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PC Cameras
Complete 10-Bit 20 MSPS
CCD Signal Processor
AD9843A
PRODUCT DESCRIPTION
The AD9843A is a complete analog signal processor for CCD
applications. It features a 20 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9843A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, input configuration, and power-
down modes.
The AD9843A operates from a single 3 V power supply, typi-
cally dissipates 78 mW, and is packaged in a 48-lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
PBLK
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
CLPOB
4dB؎6dB
CDS
CLP
2:1
MUX
BUF
CLP
AD9843A
2:1
MUX
2dB~36dB
VGA
CLP
10-BIT
ADC
10
10
6
INTERNAL
REGISTERS
OFFSET
DAC
8
BANDGAP
REFERENCE
INTERNAL
BIAS
DIGITAL
INTERFACE
INTERNAL
TIMING
DRVDD
DRVSS
DOUT
VRT
VRB
CML
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

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AD9843A–SPECIFICATIONS
GENERAL SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
Parameter
Min Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–20 +85 °C
–65
+150
°C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
2.7
3.6 V
POWER CONSUMPTION
Normal Operation
Power-Down Modes
Fast Recovery Mode
Standby
Total Power-Down
(Specified Under Each Mode of Operation)
45
5
1
mW
mW
mW
MAXIMUM CLOCK RATE
20
MHz
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Data Output Coding
10
± 0.4
10
2.0
Straight Binary
± 1.0
Bits
LSB
Bits Guaranteed
V
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
2.0 V
1.0 V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
Parameter
Symbol
Min
Typ
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
Specifications subject to change without notice.
VIH
VIL
IIH
IIL
CIN
VOH
VOL
2.1
10
10
10
2.2
Max
0.6
0.5
Unit
V
V
µA
µA
pF
V
V
–2– REV. 0

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AD9843A
CCD-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless otherwise noted.)
Parameter
Min Typ Max
Unit
Notes
POWER CONSUMPTION
78 mW See TPC 1 for Power Curves
MAXIMUM CLOCK RATE
20
MHz
CDS
Allowable CCD Reset Transient1
Max CCD Black Pixel Amplitude1
Max Input Range Before Saturation1
Max Input Range Before Saturation
Max Input Range Before Saturation
Max Output Range
Gain Resolution
Gain Range (Two’s Complement Coding)
Min Gain (CDS Gain Register Code 32)
Medium Gain (CDS Gain Code 63)
Max Gain (CDS Gain Code 31)
1.0
1.6
500
200
1.5
0.5
64
–2
4
10
mV
mV
V p-p
V p-p
V p-p
V p-p
Steps
dB
dB
dB
See Input Waveform in Note 1
With 4 dB CDS Gain
With –2 dB CDS Gain
With 10 dB CDS Gain
At Any CDS Gain Setting
See Figure 12 for CDS Gain Curve
4 dB Is Default with CDS Gain Disabled
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Register Code 91)
Max Gain (VGA Code 1023)
1.6
2.0
1024
Guaranteed
2
36
V p-p
V p-p
Steps
dB
dB
See Figure 13 for VGA Gain Curve
See Page 13 for Gain Equations
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
256
0
63.75
Steps
LSB
LSB
Measured at ADC Output
SYSTEM PERFORMANCE
Gain Accuracy, VGA Code 91 to 1023
–0.5
+0.5
Peak Nonlinearity, 500 mV Input Signal
0.1
Peak Nonlinearity, 800 mV Input Signal
0.4
Total Output Noise
0.2
Power Supply Rejection (PSR)
40
dB
%
%
LSB rms
dB
Specifications Include Entire Signal Chain
Use Equations on Page 13 to Calculate Gain
12 dB Gain Applied (4 dB CDS Gain)
8 dB Gain Applied (4 dB CDS Gain)
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
POWER-UP RECOVERY TIME
From Fast Recovery Mode
From Reference Standby Mode
From Total Shutdown Mode
From Power-Off Condition
Clocks Must Be Applied, as in Figures 5 and 6
0.1 ms
1 ms
3 ms
15 ms
NOTES
1Input Signal Characteristics defined as follows, with 4 dB CDS gain:
500mV TYP
RESET
TRANSIENT
200mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Specifications subject to change without notice.
REV. 0
–3–

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AD9843A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
Parameter
Min Typ Max
POWER CONSUMPTION
60
MAXIMUM CLOCK RATE
20
INPUT BUFFER
Gain
Max Input Range
0
1.0
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
Max Gain
2.0
1023
0
36
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
Parameter
Min Typ Max
POWER CONSUMPTION
60
MAXIMUM CLOCK RATE
20
INPUT BUFFER
(Same as AUX1-MODE)
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
Max Gain
2.0
512
0
18
ACTIVE CLAMP
Clamp Level Resolution
Clamp Level (Measured at ADC Output)
Min Clamp Level
Max Clamp Level
256
0
63.75
Specification subject to change without notice.
Unit
mW
MHz
dB
V p-p
V p-p
Steps
dB
dB
Unit
mW
MHz
V p-p
Steps
dB
dB
Steps
LSB
LSB
–4– REV. 0

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AD9843A
TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
Parameter
Symbol
Min
Typ Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
tCONV
tADC
tSHP
tSHD
tCDM
tCOB
tS1
tS2
tID
tINH
tOD
tH
48
20
7
7
4
2
0
20
10
7.0
50
25
12.5
12.5
10
20
12.5
25
3.0
14.5 16
7.6
9
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS
Parameter
With
Respect
To Min Max
Unit
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
(10 sec)
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
150 °C
300 °C
ORDERING GUIDE
Model
Temperature
Range
AD9843AJST –20°C to +85°C
Package
Description
Thin Plastic
Quad Flatpack
(LQFP)
Package
Option
ST-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9843A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–