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a
Programmable Digital
QPSK/16-QAM Modulator
AD9853
FEATURES
GENERAL DESCRIPTION
Universal Low Cost Solution for HFC Network
The AD9853 integrates a high speed direct-digital synthesizer
Return-Channel TX Function: 5 MHz–42 MHz/
(DDS), a high performance, high speed digital-to-analog con-
5 MHz–65 MHz
verter (DAC), digital filters and other DSP functions onto a
165 MHz Internal Reference Clock Capability
single chip, to form a complete and flexible digital modulator
Includes Programmable Pulse-Shaping FIR Filters and
device. The AD9853 is intended to function as a modulator in
Programmable Interpolating Filters
network applications such as interactive HFC, WLAN and
FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation
MMDS, where cost, size, power dissipation, functional integra-
Formats
tion and dynamic performance are critical attributes.
6؋ Internal Reference Clock Multiplier
The AD9853 is fabricated on an advanced CMOS process and
Integrated Reed-Solomon FEC Function
it sets a new standard for CMOS digital modulator performance.
Programmable Randomizer/Preamble Function
The device is loaded with programmable functionality and
Supports Interoperable Cable Modem Standards
Internal SINx/x Compensation
>50 dB SFDR @ 42 MHz Output Frequency (Single Tone)
Controlled Burst Mode Operation
+3.3 V to +5 V Single Supply Operation
Low Power: 750 mW @ Full Clock Speed (3.3 V Supply)
Space Saving Surface Mount Packaging
OAPPLICATIONS
BHFC Data, Telephony and Video Modems
Wireless LAN
provides a direct interface port to the AD8320, digitally-
programmable cable driver amplifier. The AD9853/AD8320
chipset forms a highly integrated, low power, small footprint
and cost-effective solution for the HFC return-path requirement
and other more general purpose modulator applications.
The AD9853 is available in a space saving surface mount pack-
age and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
SOFUNCTIONAL BLOCK DIAGRAM
LESERIAL
TEDATAIN
R-S
FEC
DATA
XOR DELAY
& MUX
ENCODER:
FSK
QPSK
DQPSK
16-QAM
D16-QAM
FIR
FILTER
INTERPOLATION
FILTER
FIR INTERPOLATION
AD9853
10
INV
SYNC
FILTER
10-BIT
10 DAC
AOUT
TO LP FILTER
AND AD8320
RANDOMIZER
PREAMBLE
INSERTION
FILTER
FILTER
GAIN
CONTROL TO
CABLE DRIVER
AMPLIFER
SINE
COSINE
DRIVER AMP
DDS
CLOCK
6؋
CONTROL FUNCTIONS
REF CLOCK IN
FEC TXENABLE RESET
ENABLE/
DISABLE
SERIAL CONTROL BUS:
32-BIT OUTPUT FREQUENCY TUNING WORD
INPUT DATA RATE/MODULATION FORMAT
FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION
FIR FILTER COEFFICIENTS
REF CLOCK MULTIPLIER ENABLE
I/Q PHASE INVERT
SLEEP MODE
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

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AD9853–SPECIFICATIONS (VS = +3.3 V ؎ 5%, RSET = 3.9 k, Reference Clock Frequency = 20.48 MHz with
6؋ REFCLK Enabled, Symbol Rate = 2.56 MS/s, = 0.25, unless otherwise noted)
Parameter
Temp Test Level Min Typ Max Units
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
6× REFCLK Disabled (+3.3 V Supply)
6× REFCLK Enabled (+3.3 V Supply)
6× REFCLK Disabled (+5 V Supply)
6× REFCLK Enabled (+5 V Supply)
Duty Cycle
Input Capacitance
Input Impedance
Full
Full
Full
Full
+25°C
+25°C
+25°C
IV
IV
IV
IV
IV
V
V
42 126
7 21
108 168
18 28
40 60
3
100
MHz
MHz
MHz
MHz
%
pF
M
DAC OUTPUT CHARACTERISTICS
Resolution
10 Bits
Full-Scale Output Current
+25°C IV
5 10 20
mA
Gain Error
+25°C I
–10 +10 % FS
Output Offset
+25°C I
10 µA
Output Offset Temperature Coefficient
Full V
50 nA/°C
Differential Nonlinearity
+25°C I
0.5 0.75 LSB
Integral Nonlinearity
+25°C I
0.5 1.5
LSB
Output Capacitance
Phase Noise @ 1 kHz Offset, 40 MHz AOUT
6× REFCLK Enabled
6× REFCLK Disabled
Voltage Compliance Range
Wideband SFDR (Single Tone):
O1 MHz AOUT
20 MHz AOUT
B42 MHz AOUT
65 MHz AOUT1
SMODULATOR CHARACTERISTICS
OI/Q Offset
Adjacent Channel Power
LError Vector Magnitude
EIn-Band Spurious Emission
5 MHz–42 MHz AOUT
TE5 MHz–65 MHz AOUT1
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
V
V
I
IV
IV
IV
IV
+25°C
+25°C
+25°C
+25°C
+25°C
IV
IV
IV
IV
IV
5
–100
–110
–0.5 +1.5
62 68
52 54
48 50
42 44
pF
dBc
dBc
V
dBc
dBc
dBc
dBc
48
44
1
2
42
40
dB
dBm
%
dBc
dBc
Passband Amplitude Ripple
+25°C V
± 0.3 dB
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulsewidth Low (tPWL)
Minimum Clock Pulsewidth High (tPWH)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (tDS)
Minimum Data Hold Time (tDH)
Minimum Clock Setup—Stop Condition (tCS)
Minimum Clock Hold—Start Condition (tCH)
RESET
Minimum TXENABLE Low to RESET Low (tTR)
Minimum RESET High to Start Condition (tRH)
FEC ENABLE
Minimum FEC ENABLE/DISABLE to TXENABLE High (tFH)
Minimum FEC ENABLE/DISABLE to TXENABLE Low (tFL)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
25 MHz
10 ns
10 ns
100 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
0 ns
0 ns
–2– REV. C

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AD9853
Parameter
Temp Test Level Min Typ Max
Units
TIMING CHARACTERISTICS (Continued)
Wake-Up Time–PLL Power-Down
Wake-Up Time–DAC Power-Down
Wake-Up Time–Digital Power-Down
Data Latency (tDL)
Minimum RESET Pulsewidth Low (tRL)
CMOS LOGIC INPUTS
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
+25°C
+25°C
+25°C
+25°C
+25°C
IV
IV
IV
IV
IV
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
I
I
I
V
1
200
5
6
10
+3.5
+3.0
3
+0.4
12
12
ms
µs
µs
Symbols
ns
V
V
V
µA
µA
pF
POWER SUPPLY2
+VS Current (+3.3 V + 5%)
Full Operating Conditions
+25°C I
184 230
mA
With PLL Power-Down Enabled
+25°C I
178 224
mA
With DAC Power-Down Enabled
With Digital Power-Down Enabled
With All Power-Down Enabled
+VS Current (+5 V + 5%)
+25°C
+25°C
+25°C
+25°C
I
I
I
I
NOTES
1Reference clock = 28 MHz with clock multiplier enabled; supply voltage = +5 V.
O2Maximum values are obtained under worst case operating modes. Typical values are valid for most applications.
BSpecifications subject to change without notice.
170 216
36 54
16 20
400 595
mA
mA
mA
mA
SEXPLANATION OF TEST LEVELS
Test Level
OI – 100% Production Tested.
LIII – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
Etesting.
TV – Parameter is a typical value only.
EVI – Devices are 100% production tested at +25°C and
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (10 sec Soldering) . . . . . . . . . . . . +300°C
guaranteed by design and characterization testing for
MQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . . 36°C/W
industrial operating temperature range.
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect device
reliability.
ORDERING GUIDE
Model
Temperature Package
Range
Description
Package
Option
AD9853AS –40°C to +85°C Metric Quad Flatpack S-44A
(MQFP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–

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AD9853
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
Pin # Pin Name
Pin Function
44-Lead Metric Quad Flatpack
(S-44A)
1, 7, 9, 10,
36, 39, 44 DGND
Digital Ground
2, 8, 37,
40, 43 DVDD
Digital Supply Voltage
3 Control Bus Clock Bit Clock for Control Bus
Data
4 Control Bus Data In Control Bus Data In
5
FEC Enable
Enables/Disables FEC
6
Address Bit
Address Bit for Control Bus
11, 26, 31 Test Data Out
Factory Use—Serial Test Data
Out
12, 13 PLL GND
PLL Ground
14 PLL VCC
Supply Voltage for PLL
44 43 42 41 40 39 38 37 36 35 34
DGND 1
DVDD 2
CONTROL
BUS CLOCK
3
CONTROL
BUS DATA IN
4
FEC ENABLE 5
ADDRESS BIT 6
DGND 7
DVDD 8
PIN 1
IDENTIFIER
AD9853
TOP VIEW
(Not to Scale)
33 CA ENABLE
32 RESET
31 TEST DATA OUT
30 TEST DATA
ENABLE
29 TEST DATA IN
28 TEST LATCH
27 TEST CLK
26 TEST DATA OUT
15 PLL Filter
PLL Loop Filter Connection
DGND 9
25 IOUTB
16, 19, 23 AGND
17 NC
18 DAC Rset
20, 22 AVDD
21 DAC Baseline
O24 IOUT
B25 IOUTB
SO27 Test CLK
28 Test Latch
L29 Test Data In
ETE30 Test Data Enable
Analog Ground
No Connect
Rset Resistor Connection
Analog Supply Voltage
DAC Baseline Voltage
Analog Current Output of the
DAC
Complementary Analog Cur-
rent Output of the DAC
Factory Use—Scan Clock
Factory Use—Scan Latch
Factory Use—Serial Test Data
In
Factory Use—Serial Test Data
Enable, Grounded for Normal
DGND 10
TEST DATA
OUT
11
12 13 14 15 16 17 18 19 20 21 22
24 IOUT
23 AGND
NC = NO CONNECT
Operation
32 RESET
Master Device Reset Function
33 CA Enable
Cable Amplifier Enable
34 CA Clock
Cable Amplifier Serial Control
Clock
35 CA Data
Cable Amplifier Serial Control
Data
38
REF CLK IN
Reference Clock Input
41 Data In
Input Serial Data Stream
42
TXENABLE
Pulse that Frames the Valid
Input Data Stream
–4– REV. C

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AD9853
Table I. Modulator Function Description
Modulation Encoding Format
FSK*, QPSK, DQPSK, 16-QAM, D16-QAM, Selectable via Control Bus
Output Carrier Frequency Range
DC – 63 MHz with +3.3 V Supply Voltage
DC – 84 MHz with +5 V Supply Voltage
Serial Input Data Rate
Evenly Divisible Fraction of Reference Clock
Pulse-Shaping FIR Filter
41 Tap, Linear Phase, 10-Bit Coefficients Fully Programmable via Control Bus
Interpolation Range
Interpolation Rate = (4/M) × (ICIC1) × (ICIC2) where: M = 2 for QPSK, M = 4 for 16-QAM
Minimum and Maximum Rates
Minimum Interpolation Rate—QPSK = 2 × 3 × 2 = 12
16-QAM = 1 × 4 × 3 = 12
Maximum Interpolation Rate—QPSK = 2 × 31 × 63 = 3906
16-QAM = 1 × 31 × 63 = 1953
These are the minimum and maximum interpolation ratios from the input data rate to the
system clock. The interpolation range is a function of the fixed interpolation factor of four
in the FIR filters, the programmed CIC filter interpolation rates (ICIC1, ICIC2), as well
Maximum Reference Clock Frequency
6× REFCLK
R-S FEC
OBSOLETEI/Q Channel Spectrum
as system timing constraints.
+3.3 V Supply: 21 MHz with 6× REFCLK enabled, 126 MHz with 6× REFCLK disabled
+5 V Supply: 28 MHz with 6× REFCLK enabled, 168 MHz with 6× REFCLK disabled
Fixed 6× reference clock multiplier, enable/disable control via control bus
Enable/disable via control bus and dedicated control pin. Control pin enable/disable function:
Logic “1” = Enable
Logic “0” = Disable
Primitive Polynomial: p(x) = x8 + x4 + x3 + x2 + 1
Code Generator Polynomial: g(x) = (x + α0)(x + α1)(x + α2) . . . (x + α2t –1)
Selectable via Control Bus
t = 0–10 (Programmable)
Codeword Length (N) = 255 max (Programmable)
N = K + 2 t (K Range = 16 K 255 – 2 t)
FEC/Randomizer can be transposed in signal chain via control bus.
I × COS + Q × SIN (default) or I × COS – Q × SIN, selectable via control bus.
Preamble Insertion
0–96 Bits, Programmable Length and Content
Randomizer
Enable/Disable Control via Control Bus
Generating Polynomial:
x6 + x5 + 1, Programmable Seed (Davic/DVB-Compliant)
or
x15 + x14 + 1, Programmable Seed (DOCSIS-Compliant)
Randomizer and FEC blocks can be transposed in signal chain, via control bus.
*In FSK mode, F0:F1 are direct DDS Cosine output. The two interpolator stages of the AD9853 are not used in the FSK mode and should be programmed for
maximum interpolation rates to reduce unnecessary current consumption. This means that Interpolator #1 should be set to a decimal value of 31, and Interpolator
#2 should be set to decimal value of 63. This is easily accomplished by programming Registers 12 and 13 (hex) with the values of FF (hex).
REV. C
–5–