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a Mixed-Signal Front-End (MxFE) Processor
for Broadband Communications
AD9860/AD9862*
FEATURES
Mixed-Signal Front-End Processor with Dual Converter
Receive and Dual Converter Transmit Signal Paths
Receive Signal Path Includes:
Two 10-/12-Bit, 64 MSPS Sampling A/D Converters
with Internal or External Independent References,
Input Buffers, Programmable Gain Amplifiers,
Low-Pass Decimation Filters, and a Digital Hilbert Filter
Transmit Signal Path Includes:
Two 12-/14-Bit, 128 MSPS D/A Converters with
Programmable Full-Scale Output Current, Channel
Independent Fine Gain and Offset Control, Digital
Hilbert and Interpolation Filters, and Digitally Tunable
Real or Complex Up-Converters
Delay-Locked Loop Clock Multiplier and Integrated
Timing Generation Circuitry Allow for Single Crystal
or Clock Operation
Programmable Output Clocks, Serial Programmable
Interface, Programmable Sigma-Delta, Three Auxiliary
DAC Outputs and Two Auxiliary ADCs with Dual
Multiplexed Inputs
APPLICATIONS
Broadband Wireless Systems
Fixed Wireless, WLAN, MMDS, LMDS
Broadband Wireline Systems
Cable Modems, VDSL, PowerPlug
Digital Communications
Set-Top Boxes, Data Modems
GENERAL DESCRIPTION
The AD9860 and AD9862 (AD9860/AD9862) are versatile
integrated mixed-signal front-ends (MxFE) that are optimized
for broadband communication markets. The AD9860/AD9862
are cost effective, mixed signal solutions for wireless or wireline
standards based or proprietary broadband modem systems where
dynamic performance, power dissipation, cost, and size are all
critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;
the AD9862 has 12-bit ADCs and 14-bit DACs.
The AD9860/AD9862 receive path (Rx) consists of two channels
that each include a high performance, 10-/12-bit, 64 MSPS analog-
to-digital converter (ADC), input buffer, Programmable Gain
Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The
Rx can be used to receive real, diversity, or I/Q data at baseband or
low IF. The input buffers provide a constant input impedance for
both channels to ease impedance matching with external com-
ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain
*Protected by U.S.Patent No. 5,969,657; other patents pending.
MxFE is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VIN+B
VIN–B
SIGDELT
AUX_DAC_A
AUX_DAC_B
AUX_DAC_C
AUX_ADC_A1
AUX_ADC_A2
AUX_ADC_B1
AUX_ADC_B2
IOUT+A
IOUT–A
IOUT+B
IOUT–B
1x PGA
ADC
BYPASSABLE LOW-PASS HILBERT
DECIMATION FILTER
FILTER
1x PGA
ADC
LOGIC LOW
-
AD9860/AD9862
AUX DAC
SPI REGISTERS
AUX DAC
AUX DAC
AUX ADC
Rx PATH
TIMING
Tx PATH
TIMING
CLOCK
DISTRIBUTION
BLOCK
DLL
1؋, 2؋, 4؋
PGA
PGA
AUX ADC
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
DAC
DAC
FS/4
FS/8
BYPASSABLE
LOW-PASS
INTERPOLATION
FILTER
NCO
HILBERT
FILTER
RxA DATA
[0:11]
RxB DATA
[0:11]
SPI
INTERFACE
OSC1
OSC2
CLKOUT1
CLKOUT2
Tx DATA
[0:13]
range for both channels. The output data bus can be multi-
plexed to accommodate a variety of interface types.
The AD9860/AD9862 transmit path (Tx) consists of two chan-
nels that contain high performance, 12-/14-bit, 128 MSPS
digital-to-analog converters (DAC), programmable gain amplifiers
(TxPGA), interpolation filters, a Hilbert filter, and digital mixers
for complex or real signal frequency modulation. The Tx latch
and demultiplexer circuitry can process real or I/Q data. Interpo-
lation rates of 2ϫ and 4ϫ are available to ease requirements on
an external reconstruction filter. For single channel systems, the
digital Hilbert filter can be used with an external quadrature
modulator to create an image rejection architecture. The two
12-/14-bit, high performance DACs produce an output signal
that can be scaled over a 20 dB range by the TxPGA.
A programmable delay-locked loop (DLL) clock multiplier and
integrated timing circuits enable the use of a single external
reference clock or an external crystal to generate clocking for all
internal blocks and also provides two external clock outputs.
Additional features include a programmable sigma-delta output,
four auxiliary ADC inputs and three auxiliary DAC outputs.
Device programmability is facilitated by a serial port interface
(SPI) combined with a register bank. The AD9860/AD9862 is
available in a space saving 128-lead LQFP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

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AD9860/AD9862–SPECIFICATIONS (VA = 3.3 V ؎ 5%, VD = 3.3 V ؎ 10%, fDAC = 128 MHz, fADC = 64 MHz
Normal Timing Mode, 2؋ DLL Setting, RSET = 4 k, 50 DAC Load,
RxPGA = +6 dB Gain, TxPGA = +20 dB Gain.)
Tx PARAMETERS
Temp
Test
Level
AD9860/AD9862
Min Typ Max
Unit
12-/14-BIT DAC CHARACTERISTICS
Resolution
Maximum Update Rate
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Negative Differential Nonlinearity (DNL)
Positive Differential Nonlinearity (+DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 6 MHz Tone
Crystal and OSC IN Multiplier Enabled at 4ϫ
Output Voltage Compliance Range
NA
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Full
NA
I
I
I
I
III
III
III
III
III
II
12/14
Bits
128 MSPS
2 20 mA
5.5
+0.5
+5.5
%FS
1 0.0 +1 %FS
1.15 1.22 1.28 V
0.5/0.5
LSB
1/2 LSB
± 1/± 3
LSB
5 pF
115
dBc/Hz
0.5
+1.5
V
TRANSMIT TxPGA CHARACTERISTICS
Gain Range
Step Size Accuracy
Step Size
25ºC
25ºC
25ºC
III
III
III
20
± 0.1
0.08
dB
dB
dB
Tx DIGITAL FILTER CHARACTERISTICS
Hilbert Filter Pass Band (<0.1 dB Ripple)
2ϫ/4ϫ Interpolator Stop Band2
Full II
Full II
12.5
38
± 38
% fDATA1
% fDATA
DYNAMIC PERFORMANCE (AOUT = 20 mA FS, f = 1 MHz)
Differential Phase
Differential Gain
AD9860 Signal-to-Noise Ratio (SNR)
AD9860 Signal-to-Noise and Distortion Ratio
AD9860 Total Harmonic Distortion (THD)
AD9860 Wideband SFDR (to Nyquist)
1 MHz Analog Out, IOUT = 2 mA
1 MHz Analog Out, IOUT = 20 mA
6 MHz Analog Out, IOUT = 20 mA
AD9860 Narrowband SFDR (1 MHz Window)
1 MHz Analog Out, IOUT = 2 mA
1 MHz Analog Out, IOUT = 20 mA
AD9862 Signal-to-Noise Ratio (SNR)
AD9862 Signal-to-Noise and Distortion Ratio
AD9862 Total Harmonic Distortion (THD)
AD9862 Wideband SFDR (to Nyquist)
1 MHz Analog Out, IOUT = 2 mA
1 MHz Analog Out, IOUT = 20 mA
6 MHz Analog Out, IOUT = 20 mA
AD9862 Narrowband SFDR (1 MHz Window)
1 MHz Analog Out, IOUT = 2 mA
1 MHz Analog Out, IOUT = 20 mA
25ºC
25ºC
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
III
III
I
I
I
III
I
III
III
I
I
I
I
III
I
III
III
I
68.2
62.5
64.4
83
68.9
64.75
64.9
83
<0.1
<1
70.7
66.1
74.5
70.6
75
75
70.2
90
72.0
69.8
75.5
70.6
76.0
76.0
70.2
90
64.0
65.0
Degree
LSB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
Rx PARAMETERS
RECEIVE BUFFER
Input Resistance (Differential)
Input Capacitance (Each Input)
Maximum Input Bandwidth (3 dB)
Analog Input Range (Best Noise Performance)
Analog Input Range (Best THD Performance)
Full III
Full III
Full III
Full II
Full II
200 W
5 pF
140 MHz
2 V p-p Diff
1 V p-p Diff
RECEIVE PGA CHARACTERISTICS
Gain Error
Gain Range
Step Size Accuracy
Step Size
Input Bandwidth (3 dB, Rx Buffer Bypassed)
25ºC
25ºC
25ºC
25ºC
25ºC
I
I
I
I
III
± 0.3
dB
19 20 21 dB
± 0.2
1
dB
dB
250 MHz
10-/12-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
NA NA
10/12
Full I
64
Bits
MHz
–2– REV. 0

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Rx PARAMETERS (continued)
Temp
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Gain Error
Aperture Delay
Aperture Uncertainty (Jitter)
Input Referred Noise
Reference Voltage Error
REFT-REFB Error (1 V)
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
AD9860 DYNAMIC PERFORMANCE (AIN = 0.5 dBFS, f = 5 MHz)
Signal-to-Noise Ratio
25C
Signal-to-Noise and Distortion Ratio
25C
Total Harmonic Distortion
25C
Spurious Free Dynamic Range
25C
AD9862 DYNAMIC PERFORMANCE (AIN = 0.5 dBFS, f = 5 MHz)
Signal-to-Noise Ratio
25C
Signal-to-Noise and Distortion Ratio
25C
Total Harmonic Distortion
25C
Spurious Free Dynamic Range
25C
CHANNEL-TO-CHANNEL ISOLATION
Tx-to-Rx (AOUT = 0 dBFS, fOUT = 7 MHz)
Rx Channel Crosstalk (f1 = 6 MHz, f2 = 9 MHz)
25ºC
25ºC
PARAMETERS
CMOS LOGIC INPUTS
Logic 1Voltage, VIH
Logic 0Voltage, VIL
Logic 1Current
Logic 0Current
Input Capacitance
25ºC
25ºC
25ºC
25ºC
25ºC
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1Voltage, VOH
Logic 0Voltage, VOL
POWER SUPPLY
Analog Supply Currents
Tx (Both Channels, 20 mA FS Output)
Tx Powered Down
Rx (Both Channels, Input Buffer Enabled)
Rx (Both Channels, Input Buffer Disabled)
Rx (32 MSPS, Low Power Mode, Buffer Disabled)
Rx (16 MSPS, Low Power Mode, Buffer Disabled)
Rx Path Powered Down
DLL
Digital Supply Current
AD9860 Both Rx and Tx Path (All Channels Enabled)
2ϫ Interpolation, fDAC = fADC = 64 MSPS
AD9862 Both Rx and Tx Path (All Channels Enabled)
2ϫ Interpolation, fDAC = fADC = 64 MSPS
Tx Path (fDAC = 128 MSPS)
Processing Blocks Disabled
4ϫ Interpolation
4ϫ Interpolation, Coarse Modulation
4ϫ Interpolation, Fine Modulation
4ϫ Interpolation, Coarse and Fine Modulation
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Test
Level
III
III
III
III
III
III
III
I
I
I
I
I
I
I
I
I
III
III
II
II
II
II
III
II
II
I
I
I
III
III
III
I
III
I
I
III
III
III
III
III
AD9860/AD9862
AD9860/AD9862
Min Typ Max
± 0.3/± 0.4
± 1.2/± 5
± 0.1
± 0.2
2.0
1.2
250
±1 ±4
59.0 60.66
56.0 58.0
76.5
70.5
70.3 81.0
62.6
62.5
77.09
64.2
64.14
79.22
85.13
73.2
>90
>80
Unit
LSB
LSB
%FSR
%FSR
ns
ps rms
µV
mV
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
DRVDD 0.7
3
DRVDD 0.6
70
2.5
275
245
155
80
5.0
12
92
104
45
90
110
110
130
0.4
12
12
0.4
76
5.0
307
6.0
112
124
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
REV. 0
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AD9860/AD9862
PARAMETERS (continued)
Temp
POWER SUPPLY (continued)
Rx Path (fADC = 64 MSPS)
Processing Blocks Disabled
Decimation Filter Enabled
Hilbert Filter Enabled
Hilbert and Decimation Filter Enabled
25ºC
25ºC
25ºC
25ºC
NOTES
1% fDATA refers to the input data rate of the digital block.
2Interpolation filter stop band is defined by image suppression of 50 dB or greater.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Test
Level
III
III
III
III
AD9860/AD9862
Min Typ Max
9
15
16
18.5
(20 pF Load)
Minimum Reset Pulsewidth Low (tRL)
Digital Output Rise/Fall Time
DLL Output Clock
DLL Output Duty Cycle
Tx/RxInterface (See Figures 11 and 12)
TxSYNC/TxIQ Setup Time (tTx1, tTx3)
TxSYNC/TxIQ Hold Time (tTx2, tTx4)
RxSYNC/RxIQ/IF to Valid Time(tRx1, tRx3)
RxSYNC/RxIQ/IF Hold Time (tRx2, tRx4)
Serial Control Bus (See Figures 1 and 2)
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulsewidth High (tHI)
Minimum Clock Pulsewidth Low (tLOW)
Maximum Clock Rise/Fall Time
Minimum Data/SEN Setup Time (tS)
Minimum SEN/Data Hold Time (tH)
Minimum Data/SCLK Setup Time (tDS)
Minimum Data Hold Time (tDH)
Output Data Valid/SCLK Time (tDV)
AUXILARY ADC
Conversion Rate
Input Range
Resolution
AUXILARY DAC
Settling Time
Output Range
Resolution
ADC TIMING
Latency (All Digital Processing Blocks Disabled)
DAC Timing
Latency (All Digital Processing Blocks Disabled)
Latency (2ϫ Interpolation Enabled)
Latency (4ϫ Interpolation Enabled)
Additional Latency (Hilbert Filter Enabled)
Additional Latency (Coarse Modulation Enabled)
Additional Latency (Fine Modulation Enabled)
Output Settling Time (TST) (to 0.1%)
Specifications subject to change without notice.
Temp
NA
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Full
Full
Full
Full
Full
Full
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Test
Level
NA
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
AD9860/AD9862
Min Typ Max
5
2.8 4
32 128
50
3
3
5.2
0.2
16
30
30
1
25
0
25
0
30
1.25
3
10
8
3
8
7
3
30
72
36
5
8
35
Unit
mA
mA
mA
mA
Unit
Clock Cycles
ns
MHz
%
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
ns
ns
MHz
V
Bits
ms
V
Bits
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ns
–4– REV. 0

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ABSOLUTE MAXIMUM RATINGS1
Power Supply (VAS, VDS) . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Digital Inputs . . . . . . . . . . . . . . . . 0.3 V to DRVDD + 0.3 V
Analog Inputs . . . . . . . . . . . . . . 0.3 V to AVDD (IQ) + 0.3 V
Operating Temperature2 . . . . . . . . . . . . . . . . . 40؇C to +70؇C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150؇C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65؇C to +150؇C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300؇C
NOTES
1Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional operability
under any of these conditions is not necessarily implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect device
reliability.
2The AD9860/AD9862 have been characterized to operate over the industrial
temperature range (40؇C to +85؇C) when operated in Half Duplex Mode.
AD9860/AD9862
EXPLANATION OF TEST LEVELS
I. Devices are 100% production tested at 25ºC and guaranteed
by design and characterization testing for the extended
industrial temperature range (40ºC to +70ºC).
II. Parameter is guaranteed by design and/or characterization
testing.
III. Parameter is a typical value only.
NA. Test level definition is not applicable.
THERMAL CHARACTERISTICS
Thermal Resistance
128-Lead LQFP JA = 29ºC/W
Model
Temperature Range
ORDERING GUIDE
Package Description
Package Option
AD9860BST
AD9862BST
AD9860PCB
AD9862PCB
40C to +70C*
40C to +70C*
128-Lead Low Profile Plastic Quad Flatpack (LQFP)
128-Lead Low Profile Plastic Quad Flatpack (LQFP)
Evaluation Board with AD9860
Evaluation Board with AD9862
ST-128B
ST-128B
*The AD9860/AD9862 have been characterized to operate over the industrial temperature range (40 ؇C to +85؇C) when operated in Half Duplex Mode.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–