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FEATURES
10 MHz–300 MHz Input Frequency
Baseband (I/Q) Digital Output
10 kHz–150 kHz Output Signal Bandwidth
12 dB SSB NF
> –1 dBm IIP3 (High IIP3 Mode)
25 dB Continuous AGC Range + 16 dB Gain Step
Support for LO and Sampling Clock Synthesis
Programmable Decimation Rate, Output Format, AAF
Cutoff, AGC and Synthesizer Settings
360 Input Impedance
2.7 V–3.6 V Supply Voltage
Low Current: 42 mA Typ (High IIP3 Mode),
30 mA Typ (Low IIP3, Fixed Gain Mode)
48-Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Portable and Mobile Radio Products
Digital UHF/VHF FDMA Products
TETRA
IF Digitizing Subsystem
AD9870
PRODUCT DESCRIPTION
The AD9870 is a general-purpose IF subsystem that digitizes a
low-level 10 MHz–300 MHz IF input with a bandwidth of up to
150 kHz. The signal chain of the AD9870 consists of a low-noise
amplifier, a mixer, a variable gain amplifier with integral antialias
filter, a bandpass sigma-delta analog-to-digital converter, and a
decimation filter with programmable decimation factor. An auto-
matic gain control (AGC) circuit provides the AD9870 with
25 dB of continuous gain adjustment. The high dynamic range
of the bandpass sigma-delta converter allows the AD9870 to
cope with blocking signals that are as much as 70 dB stronger
than the desired signal. Auxiliary blocks include clock and LO
synthesizers as well as a serial peripheral interface (SPI) port.
The SPI port programs numerous parameters of the AD9870,
including the synthesizer divide ratios, the AGC attack and decay
times, the AGC target signal level, the decimation factor, the
output data format, the 16 dB attenuator, and the bias currents of
several blocks. Reducing bias currents allows the user to reduce
power consumption at the expense of reduced performance.
FUNCTIONAL BLOCK DIAGRAM
AD9870
–16dB
IFIN LNA
FREF
LO
SYNTH
DAC AGC
VGA /
AAF
-ADC
fCLK = 18MHz
DECIMATION
FILTER
FORMATTING/SSI
SAMP CLOCK
SYNTHESIZER
VOLTAGE
REFERENCE
CONTROL LOGIC
SPI
DOUTA
DOUTB
FS
CLKOUT
LO VCO AND
LOOP FILTER
CLK VCO AND
LOOP FILTER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001

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AD9870–SPECIFICATIONS (VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ =
VDDP = 5.0 V, CLK = 18 MSPS, FIF = 73.35 MHz, FLO = 71.1 MHz, unless otherwise noted.)
Parameter
Conditions1
Min Typ
Max
Unit
OVERALL
Analog Supply Voltage
(VDDA, VDDF, VDDI)
Digital Supply Voltage
(VDDD, VDDC, VDDL)
Interface Supply Voltage
(VDDH)
Charge Pump Supply Voltage
(VDDP, VDDQ)
Total Current
SSB Noise Figure @ Max VGA Gain
Input Third-Order Intercept (IIP3)
Input Impedance
Gain Variation Over Temperature
High IIP3 Setting
High IIP3 Setting
Low IIP3 Setting
High IIP3 Setting
Low IIP3 Setting
2.7 3.0
2.7 3.0
1.8
2.7 3.0
42
12
12
–5 –1
–10
360
0.6
3.6
3.6
3.6
5.5
50.6
V
V
V
V
mA
dB
dB
dBm
dBm
dB
PREAMP + MIXER
Maximum Input and LO Frequencies
300 MHz
LO SYNTHESIZER
LO Input Frequency
LO Input Amplitude
FREF (Reference) Frequency
FREF Input Amplitude
Minimum Charge Pump Output Current
Maximum Charge Pump Output Current
Charge Pump Output Compliance Voltage2
Synthesizer Resolution
Programmable in 0.625 mA Steps
Programmable in 0.625 mA Steps
7.75
0.3
0.1
0.3
0.625
5.000
0.25
6.25
300
1.0
25
3
VDDP – 0.25
MHz
V p-p
MHz
V p-p
mA
mA
V
kHz
CLOCK SYNTHESIZER
CLK Input Frequency
CLK Input Amplitude
Minimum Charge Pump Output Current
Maximum Charge Pump Output Current
Charge Pump Output Compliance Voltage2
Synthesizer Resolution
Clock VCO Off
Programmable in 0.625 mA Steps
Programmable in 0.625 mA Steps
13
0.3
0.625
5.000
0.25
2.2
18
VDDQ – 0.25
MHz
V p-p
mA
mA
V
kHz
SIGMA-DELTA ADC
Resolution
Clock Frequency (fCLK)
Center Frequency
Dynamic Range
Passband Gain Variation
BW = 10 kHz
16
13 18
fCLK/8
88
0.5
Bits
MHz
MHz
dB
dB
DECIMATOR
Decimation Factor
Passband Width
Passband Gain Variation
Alias Attenuation
Programmable in Steps of 60
60
50
85
960
1
%
dB
dB
GAIN CONTROL
Programmable Gain Step
AGC Gain Range (Continuous)
AGC Attack Time
Programmable
16
18 25
40
60
7000
dB
dB
µs
SPI
PC Clock Frequency
PD Hold Time
10 MHz
10 ns
SSI
CLKOUT Frequency
Output Rise/Fall Time
CMOS Output Mode, Drive Strength = 0
CMOS Output Mode, Drive Strength = 1
CMOS Output Mode, Drive Strength = 2
CMOS Output Mode, Drive Strength = 3
1
18 MHz
120 ns
45 ns
16 ns
10 ns
OPERATING TEMPERATURE RANGE
Basic Functions
Meets All Specifications
–40 +95 °C
–40 +85 °C
NOTES
1Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, 25 pF load on SSI output pins: VDDx = 3.0 V.
2Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
Specifications subject to change without notice.
–2– REV. 0

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AD9870
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
Min Max
Unit
VDDF, VDDA, VDDC, VDDD, VDDH,
VDDL, VDDI
VDDF, VDDA, VDDC, VDDD, VDDH,
VDDL, VDDI
VDDP, VDDQ
GNDF, GNDA, GNDC, GNDD, GNDH
GNDL, GNDI, GNDQ, GNDP, GNDS
MXOP, MXON, LOP, LON, IFIN,
CXIF, CXVL, CXVM
PC, PD, PE, CLKOUT, DOUTA,
DOUTB, FS, SYNCB
IF2N, IF2P, GCP, GCN
VREFP, VREFN, VCM
IOUTC
IOUTL
CLKP, CLKN
FREF
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
GNDF, GNDA, GNDC, GNDD, GNDH
GNDL, GNDI, GNDS
VDDR, VDDA, VDDC, VDDD, VDDH,
VDDL, VDDI
GNDP, GNDQ
GNDF, GNDA, GNDC, GNDD, GNDH
GNDL, GNDI, GNDQ, GNDP, GNDS
GNDI
GNDH
GNDF
GNDA
GNDQ
GNDP
GNDC
GNDL
–0.3
–4.0
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
+4.0
+4.0
+6.0
+0.3
VDDI + 0.3
VDDH + 0.3
VDDF + 0.3
VDDA + 0.3
VDDQ + 0.3
VDDP + 0.3
VDDC + 0.3
VDDL + 0.3
150
+150
300
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
θJA = 91°C/W
θJC = 28°C/W
Model
AD9870
AD9870EB
Temperature Range
–40°C to +85°C
ORDERING GUIDE
Package Description
48-Lead Thin Plastic Quad Flatpack (LQFP)
Evaluation Board
Package Option
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9870 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–

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AD9870
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
MXOP 1
MXON 2
GNDF 3
IF2N 4
IF2P 5
VDDF 6
GCP 7
GCN 8
VDDA 9
GNDA 10
VREFP 11
VREFN 12
PIN 1
IDENTIFIER
AD9870
TOP VIEW
(Not to Scale)
36 GNDL
35 FREF
34 GNDS
33 SYNCB
32 GNDH
31 FS
30 DOUTB
29 DOUTA
28 CLKOUT
27 VDDH
26 VDDD
25 PE
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
Pin Mnemonic
1 MXOP
2 MXON
3 GNDF
4 IF2N
5 IF2P
6 VDDF
7 GCP
8 GCN
9 VDDA
10 GNDA
11 VREFP
12 VREFN
13 VCM
14 VDDQ
15 IOUTC
16 GNDQ
17 VDDC
18 GNDC
19 CLKP
20 CLKN
21 GNDS
22 GNDD
23 PC
24 PD
Mixer Output, Positive
Mixer Output, Negative
Ground for VGA
Second IF Input (to VGA), Negative
Second IF Input (to VGA), Positive
Positive Power Supply for Antialias Filter/VGA
Filter Capacitor for VGA Gain Control, Positive
Filter Capacitor for VGA Gain Control, Negative
Positive Power Supply for ADC
Ground for ADC
Voltage Reference, Positive
Voltage Reference, Negative
Common-Mode Voltage (Requires 20 kto GNDA)
Pos. Power Supply for Clock Synth. Charge Pump
Clock Synthesizer Charge Pump Output Current
Ground for Clock Synthesizer Charge Pump
Positive Power Supply for Clock Synthesizer
Ground for Clock Synthesizer
Sampling Clock Input/Clock VCO Tank, Positive
Sampling Clock Input/Clock VCO Tank, Negative
Substrate Ground
Ground for Digital Functions
Clock Input for SPI Port
Data I/O for SPI Port
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PE
VDDD
VDDH
CLKOUT
DOUTA
DOUTB
FS
GNDH
SYNCB
GNDS
FREF
GNDL
GNDP
IOUTL
VDDP
VDDL
CXVM
LON
LOP
CXVL
GNDI
CXIF
IFIN
VDDI
Description
Enable Input for SPI Port
Positive Power Supply for Internal Digital Functions
Positive Power Supply for Digital Interface
Clock Output for SSI Port
Data Output for SSI Port
Data Output for SSI Port, Unused
Frame Sync for SSI Port
Ground for Digital Interface
Resets the SSI and Decimator Counters
Substrate Ground
Reference Frequency Input for Both Synthesizers
Ground for LO Synthesizer
Ground for LO Synthesizer Charge Pump
LO Synthesizer Charge Pump Output Current
Positive Power Supply for LO Synth. Charge Pump
Positive Power Supply for LO Synthesizer
External Capacitor for Mixer Bias
LO Input to Mixer and LO Synthesizer, Negative
LO Input to Mixer and LO Synthesizer, Positive
External Capacitor for Preamp Power Supply
Ground for Mixer and Preamp
External Capacitor for Preamp Bias
First IF Input (to Preamp)
Positive Power Supply for Mixer and Preamp
–4– REV. 0

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AD9870
SERIAL PERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed
below as well as to read back their contents. Table I provides a list of the registers that may be programmed through the SPI port.
Addresses and default values are given in hexadecimal form.
Table I. SPI Address Map
Address Bit
(Hex) Breakdown
Width Default Value Name
Description
POWER CONTROL REGISTERS
0x00 (7:0)
8 0xFF
STBY
Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, VGA, ADC).
0x01
(7:6)
(5:4)
(3:2)
(1:0)
20
20
20
21
LNAB
MIXB
CKOB
ADCB
LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA).
Mixer Bias Current (0 = 1 mA, 1 = 2 mA, 2 = 3 mA, 3 = 4 mA).
CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.53 mA, 3 = 0.85 mA).
ADC Amplifier Bias (0 = 2.4 mA, 1 = 3.2 mA, 2 = 4.0 mA, 3 = 4.8 mA).
0x02 (7:0)
8 0x00
TEST
Factory Test Mode.
AGC
0x03
(7)
(6:0)
10
7 0x3F
ATTEN
Apply 16 dB attenuation in the front end.
AGCG(14:8) AGC Gain Setting (7 MSBs of a 15-bit two’s-complement word).
0x04 (7:0)
8 0xFF
AGCG(7:0) AGC Gain Setting (8 LSBs of a 15-bit two’s-complement word).
Default corresponds to maximum gain.
0x05
(7:4)
(3:0)
40
40
AGCA
AGCD
AGC Attack Time Setting. Default yields 50 Hz raw loop bandwidth.
AGC Decay Time Setting. Default is decay time = attack time.
0x06
(7:4)
(3:0)
(2:0)
40
40
30
AGCO
AGCD
AGCR
AGC Overload Update Setting. Default is slowest update.
Fast AGC (Minimizes resistance seen between GCN and GCP).
AGC Enable/Reference Level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below clip).
DECIMATION FACTOR
0x07 (3:0)
44
M Decimation Factor = 60 × (M + 1). Default is decimate-by-300.
LO SYNTHESIZER
0x08 (5:0)
6 0x00
LOR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word).
0x09 (7:0)
0x0A
(7:5)
(4:0)
8 0x38
3 0x5
5 0x00
LOR(7:0)
LOA
LOB(12:8)
Reference Frequency Divisor (8 LSBs of a 14-Bit Word).
Default (56) Yields 300 kHz from fREF = 16.8 MHz.
“A” Counter (Prescaler Control Counter).
“B” Counter MSBs (5 MSBs of a 13-Bit Word).
Default LOA and LOB Values Yield 300 kHz from 73.35 MHz–2.25 MHz.
0x0B (7:0)
8 0x1D
LOB(7:0) “B” Counter LSBs (8 LSBs of a 13-Bit Word).
0x0C
(6)
(5)
(4:2)
(1:0)
10
10
30
20
LOF
LOINV
LOI
LOTM
Enable Fast Acquire.
Invert Charge Pump (0 = Pump_Up IOUTL Sources Current).
Charge Pump Current in Normal Operation. IPUMP = (LOI + 1) × 0.625 mA.
Manual Control of LO Charge Pump (3 = Off, 2 = Down, 1 = Up, 0 = Normal).
0x0D (3:0)
4 0x0
LOFA(13:8) LO Fast Acquire Time Unit (4 MSBs of a 14-Bit Word).
0x0E (7:0)
8 0x04
LOFA(7:0) LO Fast Acquire Time Unit (8 LSBs of a 14-Bit Word).
CLOCK SYNTHESIZER
0x10 (5:0)
6 00
CKR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word).
0x11 (7:0)
8 0x38
CKR(7:0)
Reference Frequency Divisor (8 LSBs of a 14-Bit Word).
Default Yields 300 kHz from fREF =16.8 MHz.
Min = 3, Max = 16383.
0x12 (4:0)
5 0x00
CKN(12:8) Synthesized Frequency Divisor (5 MSBs of a 13-Bit Word).
REV. 0
–5–