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FEATURES
140 MSPS Maximum Conversion Rate
500 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
400 ps p-p PLL Clock Jitter
Power-Down Mode
3.3 V Power Supply
2.5 V to 3.3 V Three-State CMOS Outputs
Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 570 mW Typical
Internal PLL Generates CLOCK from HSYNC
Serial Port Interface
Fully Programmable
Supports Alternate Pixel Sampling for Higher-
Resolution Applications
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
100 MSPS/140 MSPS
Analog Flat Panel Interface
AD9884A
FUNCTIONAL BLOCK DIAGRAM
RIN CLAMP
GIN CLAMP
BIN CLAMP
HSYNC
COAST
CLAMP
CKINV
CKEXT
CLOCK
GENERATOR
0.15V
8
A/D
8
A/D
8
A/D
2
AD9884A
8
8
ROUTA
ROUTB
8
GOUTA
8
GOUTB
8
BOUTA
8
BOUTB
DATACK
HSOUT
CONTROL
REF
REFIN
FILT SOGIN SOGOUT SDA SCL A0 A1 PWRDN REFOUT
GENERAL DESCRIPTION
The AD9884A is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports display resolutions of up to 1280 × 1024 (SXGA) at
75 Hz with sufficient input bandwidth to accurately acquire and
digitize each pixel.
To minimize system cost and power dissipation, the AD9884A
includes an internal 1.25 V reference, PLL to generate a pixel
clock from HSYNC, and programmable gain, offset and clamp
circuits. The user provides only a 3.3 V power supply, analog
input, and HSYNC signals. Three-state CMOS outputs may be
powered by a supply between 2.5 V and 3.3 V.
The AD9884A’s on-chip PLL generates a pixel clock from the
HSYNC input. Pixel clock output frequencies range from
20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p
relative to the input reference. When the COAST signal is pre-
sented, the PLL maintains its output frequency in the absence
of HSYNC. A 32-step sampling phase adjustment is provided.
Data, HSYNC and Data Clock output phase relationships are
always maintained. The PLL can be disabled and an external
clock input provided as the pixel clock.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a two-wire serial port.
Fabricated in an advanced CMOS process, the AD9884A is
provided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over a 0°C to +70°C temperature range.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001

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AD9884A* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Data Sheet
• AD9884A: 100 MSPS/140 MSPS Analog Flat Panel
Interface Data Sheet
Tools and Simulations
• AD9984 CCD PLL Setting
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Technical Articles
• Analysis of Common Failures of HDMI CT
Design Resources
• AD9884A Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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Technical Support
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AD9884A–SPECIFICATIONS (VD = 3.3 V, VDD = 3.3 V, PVD = 3.3 V, ADC Clock Frequency = Maximum, PLL
Clock Frequency = Maximum, Control Registers Programmed to Default State)
Parameter
Temp
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
25°C
Full
25°C
Full
Full
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
Full
Full
25°C
25°C
Full
Full
Full
Full
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full
Full
SWITCHING PERFORMANCE
Maximum Conversion Rate Full
Minimum Conversion Rate Full
Data to Clock Skew, tSKEW
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
HSYNC Input Frequency
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Maximum PLL Clock Rate Full
Minimum PLL Clock Rate
Full
PLL Jitter
25°C
Full
Sampling Phase Tempco
Full
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
Full
Full
Full
Full
25°C
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle
DATACK, DATACK
Output Coding
Full
Full
Full
Test
Level
I
VI
I
VI
VI
VI
VI
V
I
VI
VI
VI
VI
VI
V
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
VI
VI
VI
VI
V
VI
VI
IV
AD9884AKS-100
Min Typ
Max
8
± 0.5
± 0.5
Guaranteed
± 1.0
± 1.0
± 1.25
± 1.75
0.5
1.0
100
1
1
7 50
1.5 5.0
22 23.5 25
1.20 1.25
± 50
1.30
100
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
100
400
15
10
+2.0
110
20
7001
10001
2.5
3
0.8
–1.0
+1.0
VDD – 0.1
45 50
Binary
0.1
55
AD9884AKS-140
Min Typ
Max
8
Unit
Bits
± 0.5
± 0.8
Guaranteed
+1.15/–1.0
+1.25/–1.0
± 1.4
± 2.5
LSB
LSB
LSB
LSB
0.5
1.0
280
1
1
7 50
1.5 5.0
22 23.5 25
1.20 1.25 1.30
± 50
140
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
140
475
15
10
+2.0
110
20
7502
10002
2.5
3
0.8
–1.0
+1.0
VDD – 0.1
45 50
Binary
0.1
55
V p-p
V p-p
ppm/°C
µA
µA
mV
%FS
%FS
V
ppm/°C
MSPS
MSPS
ns
µs
µs
µs
µs
µs
ns
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
µA
µA
pF
V
V
%
–2– REV. C

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AD9884A
Parameter
Test AD9884AKS-100
Temp Level Min Typ Max
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current (VD)
IDD Supply Current (VDD)3
IPVD Supply Current (PVD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
IV
IV
IV
V
V
V
VI
VI
VI
3.0
2.2
3.0
3.3 3.6
3.3 3.6
3.3 3.6
125
33
15
570 675
2.0 25
6.6 82.5
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)4
(Without Harmonics)
fIN = 40.7 MHz
Crosstalk
25°C
25°C
25°C
25°C
Full
Full
V
V
V
I
V
V
500
2
1.5
44.0 46.5
46.0
60
THERMAL CHARACTERISTICS
θJC–Junction-to-Case
Thermal Resistance
θJA–Junction-to-Ambient
Thermal Resistance
V
V
8.4
35
NOTES
1VCORNGE = 01, CURRENT = 001, PLLDIV = 169310.
2VCORNGE = 10, CURRENT = 110, PLLDIV = 160010.
3DEMUX = 1; DATACK and DATACK load = 15 pF; Data load = 5 pF.
4Using external pixel clock.
Specifications subject to change without notice.
AD9884AKS-140
Min Typ Max
Unit
3.0 3.3 3.6 V
2.2 3.3 3.6 V
3.0 3.3 3.6 V
135 mA
47 mA
15 mA
650 775 mW
2.0 25 mA
6.6 82.5 mW
500
2
1.5
43.5 46.2
45.0
60
MHz
ns
ns
dB
dB
dBc
8.4 °C/W
35 °C/W
ORDERING GUIDE
Model
Temperature Package
Range
Description
Package
Option
AD9884AKS-140 0°C to 70°C
AD9884AKS-100 0°C to 70°C
AD9884A/PCB 25°C
MQFP
S-128
MQFP
S-128
Evaluation Board
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified
temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
ABSOLUTE MAXIMUM RATINGS*
VD, PVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4 V
PVD to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to –0.5 V
REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9884A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–

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AD9884A
Table I. Package Interconnections
Signal Type Name
Inputs
RAIN
GAIN
BAIN
HSYNC
COAST
CLAMP
SOGIN
CKEXT
CKINV
Outputs
DRA7-0
DRB7-0
DGA7-0
DGB7-0
DBA7-0
DBB7-0
DATACK
DATACK
HSOUT
SOGOUT
Control
SDA
SCL
A0, A1
PWRDN
Analog Interface REFOUT
REFIN
FILT
Power Supply VD
VDD
PVD
GND
No Connect NC
Function
Value
Package Pin
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
0.5 V to 1.0 V FS
0.5 V to 1.0 V FS
0.5 V to 1.0 V FS
7
15
22
Horizontal Sync Input
3.3 V CMOS
Clock Generator Coast Input (Optional) 3.3 V CMOS
External Clamp Input (Optional)
3.3 V CMOS
Sync On Green Slicer Input (Optional) 0.5 V to 1.0 V FS
40
41
28
14
External Clock Input (Optional)
Sampling Clock Inversion (Optional)
3.3 V CMOS
3.3 V CMOS
44
27
Data Output, Red Channel, Port A
Data Output, Red Channel, Port B
Data Output, Green Channel, Port A
Data Output, Green Channel, Port B
Data Output, Blue Channel, Port A
Data Output, Blue Channel, Port B
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
105–112
95–102
85–92
75–82
65–72
55–62
Data Output Clock
Data Output Clock Complement
3.3 V CMOS
3.3 V CMOS
115
116
Horizontal Sync Output
Sync On Green Slicer Output
3.3 V CMOS
3.3 V CMOS
117
118
Serial Data I/O
Serial Interface Clock
Serial Port Address LSBs
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
29
30
31, 32
Power-Down Control Input
3.3 V CMOS
125
Internal Reference Output
Reference Input
External Filter Connection
1.25 V
1.25 V ± 10%
126
127
45
Main Power Supply
Digital Output Power Supply
Clock Generator Power Supply
Ground
3.3 V ± 10%
2.5 V to 3.3 V ± 10%
3.3 V ± 10%
0V
4, 8, 10, 11, 16, 18, 19, 23, 25,
124, 128
54, 64, 74, 84, 94, 104, 114, 120
33, 34, 43, 48, 50
5, 6, 9, 12, 13, 17, 20, 21, 24, 26,
35, 39, 42, 47, 49, 51, 52, 53, 63,
73, 83, 93, 103, 113, 119, 121,
122, 123
1–3, 36–38, 46
–4– REV. C