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Data Sheet
FEATURES
170 MSPS maximum conversion rate
500 MHz programmable analog bandwidth
0.5 V to 1.0 V analog input range
Less than 450 ps p-p PLL clock jitter at 170 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
2:1 analog input mux
4:2:2 output format mode
Midscale clamping
Power-down mode
Low power: <1 W typical at 170 MSPS
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
GENERAL DESCRIPTION
The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 170 MSPS encode rate
capability and full-power analog bandwidth of 500 MHz supports
resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface that has a 170 MHz triple ADC with
an internal 1.25 V reference phase-locked loop (PLL) to generate a
pixel clock from HSYNC and COAST; midscale clamping; and
programmable gain, offset, and clamp controls. The user provides
only a 3.3 V power supply, analog input, and HSYNC and COAST
signals. Three-state CMOS outputs can be powered from 2.5 V
to 3.3 V.
The on-chip PLL of the AD9888 generates a pixel clock from the
HSYNC and COAST inputs. Pixel clock output frequencies
100 MSPS/140 MSPS/170 MSPS
Analog Flat Panel Interface
AD9888
RAIN0
RAIN1
GAIN0
GAIN1
BAIN0
BAIN1
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
COAST
CLAMP
CKINV
CKEXT
FILT
SCL
SDA
A0
FUNCTIONAL BLOCK DIAGRAM
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
CLAMP
CLAMP
CLAMP
ADC 8
ADC 8
ADC 8
8
8
8
8
8
8
2
SYNC
PROCESSING
AND CLOCK
GENERATION
REF
DRA[7:0]
DRB[7:0]
DGA[7:0]
DGB[7:0]
DBA[7:0]
DBB[7:0]
DATACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
SERIAL REGISTER
AND
POWER MANAGEMENT
AD9888
Figure 1.
range from 10 MHz to 170 MHz. PLL clock jitter is typically
less than 450 ps p-p at 170 MSPS. When the COAST signal is
presented, the PLL maintains its output frequency in the absence of
HSYNC. A sampling phase adjustment is provided. Data, HSYNC,
and clock output phase relationships are maintained. The PLL
can be disabled, and an external clock input can be provided as
the pixel clock. The AD9888 also offers full sync processing for
composite sync and sync-on-green applications.
A CLAMP signal is generated internally or can be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a 2-wire serial port.
Fabricated in an advanced CMOS process, the AD9888 is
provided in a space-saving, 128-lead, MQFP, surface-mount,
plastic package and is specified over the 0°C to 70°C temperature
range. The AD9888 is also available in a Pb-free package.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.

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AD9888* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Documentation
Data Sheet
• AD9888: 100/140/170/205 MSPS Analog Flat Panel
Interface Data Sheet
Software and Systems Requirements
• AD988x Evaluation Tools Software Program
Tools and Simulations
• AD9888 CCD PLL Setting
• AD9888 IBIS Models
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Technical Articles
• Analysis of Common Failures of HDMI CT
Design Resources
• AD9888 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
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Technical Support
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AD9888
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 3 
Specifications..................................................................................... 4 
Absolute Maximum Ratings............................................................ 6 
Explanation of Test Levels ........................................................... 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Design Guide................................................................................... 12 
General Description................................................................... 12 
Input Signal Handling................................................................ 12 
Sync Processing Overview ........................................................ 12 
HSYNC and VSYNC Inputs...................................................... 12 
Serial Control Port ..................................................................... 12 
Output Signal Handling............................................................. 12 
Clamping ..................................................................................... 12 
Gain and Offset Control............................................................ 13 
Sync-on-Green Input ................................................................. 14 
Clock Generation ....................................................................... 14 
Alternate Pixel Sampling Mode ................................................ 16 
Timing.......................................................................................... 17 
2-Wire Serial Register Map ........................................................... 21 
2-Wire Serial Control Register Details ........................................ 24 
Data Sheet
Chip Identification ..................................................................... 24 
PLL Divider Control .................................................................. 24 
Clock Generator Control .......................................................... 24 
Clamp Timing............................................................................. 24 
HSYNC Pulse Width.................................................................. 25 
Input Gain ................................................................................... 25 
Input Offset ................................................................................. 25 
Sync Control ............................................................................... 25 
Input Control .............................................................................. 26 
Mode Control 1 .......................................................................... 29 
2-Wire Serial Control Port ............................................................ 31 
Data Transfer via Serial Interface............................................. 31 
Sync Processing .......................................................................... 32 
Sync Slicer.................................................................................... 33 
Sync Separator ............................................................................ 33 
PCB Layout Recommendations.................................................... 34 
Analog Interface Inputs ............................................................. 34 
Power Supply Bypassing ............................................................ 34 
PLL ............................................................................................... 34 
Outputs (Both Data and Clocks).............................................. 34 
Digital Inputs .............................................................................. 35 
Voltage Reference ....................................................................... 35 
Outline Dimensions ....................................................................... 36 
Ordering Guide .......................................................................... 36 
Rev. C | Page 2 of 36

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Data Sheet
REVISION HISTORY
12/11—Rev. B to Rev. C
Updated Format.................................................................. Universal
Deleted AD9888AKSZ-205 Model .................................. Universal
Changed Maximum Conversion Rate from
205 MSPS to 170 MSPS ............................................ Throughout
Changes to Figure 1 and General Description ..............................1
Deleted AD9888KS-205 Columns, Changes to tDHO Parameter,
Table 1.............................................................................................4
Changes to Output Voltage, Low (VOL) Parameter, Table 1;
Moved Figure 2..............................................................................5
Changes to Table 2 and ESD Caution Section...............................6
Changes to Table 3 ............................................................................8
Changes to Table 4 ............................................................................9
Changes to YUV Clamping Section and to Gain and Offset
Control Section............................................................................13
Changes to Sync-on-Green Input Section and to Figure 8........14
Changes to Table 5 ..........................................................................15
Moved Figure 10, Figure 11, and Figure 12 .................................16
Changes to Captions of Figure 16 Through Figure 25 ...............17
Changes to Table 8 ..........................................................................21
Changes to Chip Identification Section .......................................24
Changes to Table 14 and Table 17 .................................................26
Changes to Address 0x10[7:3]—Sync-on-Green Slicer Threshold
Section and to Address 0x11[7:0]—Sync Separator Threshold
Section ..........................................................................................27
Changes to Address 0x14[6]—Active HSYNC (AHS) Section,
Added Table 29, Changes to Address 0x14[3]—Active
VSYNC (AVS) Section, Added Table 33, Changes to
Table 34.........................................................................................28
Changes to Address 0x15[6]—Output Mode Section and to
Address 0x15[5]—A/B Invert Control (OUTPHASE)
Section ..........................................................................................29
Moved Figure 26..............................................................................31
AD9888
Moved Figure 27..............................................................................32
Changes to Outputs (Both Data and Clocks) Section................34
Changes to Voltage Reference Section .........................................35
Updated Outline Dimensions........................................................36
Changes to Ordering Guide...........................................................36
3/03—Rev. A to Rev. B
Changes to Specifications ...............................................................2
Changes to Pin Configuration.........................................................4
Changes to Table II .........................................................................11
Changes to Table IV........................................................................11
Changes to Figure 20 ......................................................................16
Changes to Figure 22 ......................................................................17
Changes to Table V .........................................................................17
Changes to Table VI........................................................................20
Changes to Table XIII .....................................................................22
Changes to Clamp Input Signal Source Section..........................22
Changes to Table XXX....................................................................24
Added text to Outputs (Both Data and Clocks) Section ...........29
Updated Outline Dimensions........................................................30
1/02—Rev. 0 to Rev. A.
Change to Title–Part Name .............................................................1
Change to Pin Function Detail, CKINV Section..........................7
Change to Figure 13..........................................................................5
Change to Figure 14........................................................................15
Change to Figure 15........................................................................16
Change to Figure 16........................................................................16
Change to Figure 17........................................................................17
Change to Figure 18 .......................................................................17
Change to Figure 21........................................................................19
Change to Figure 22........................................................................19
7/01—Revision 0: Initial Version
Rev. C | Page 3 of 36

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AD9888
Data Sheet
SPECIFICATIONS
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Temperature Coefficient
Input Bias Current
Input Capacitance
Input Resistance
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock to Data Skew (tskew)
I2C Timing2
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter3
Sampling Phase Temperature
Coefficient
Temp
Test
Level
AD9888KSZ-100/-1401
Min Typ
8
Max
AD9888KSZ-170
Min Typ
8
Max
Unit
Bits
25°C I
Full VI
25°C I
Full VI
25°C I
±0.5 ±1.25/−1.0
+1.35/−1.0
±0.5 ±2.0
±2.5
Guaranteed
±0.6 +1.25/−1.0
+1.50/−1.0
±0.75
±2.25
±2.75
Guaranteed
LSB
LSB
LSB
LSB
25°C I
25°C I
25°C V
25°C IV
Full IV
Full V
Full IV
Full VI
Full VI
Full VI
Full VI
Full V
Full VI
Full IV
Full IV
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full IV
Full VI
Full IV
25°C IV
Full IV
Full IV
1.0
100
3
1
7
2.5
44 49
1.20 1.25
±50
100/140
−1.25
4.7
4.0
250
4.7
4.0
250
4.7
4.0
15
100/140
470
15
0.5
1
2
90
9.0
53
1.30
10
+1.25
110
10
700
1000
1.0
100
3
1
7
2.5
44 49
1.20 1.25
±50
170
−1.25
4.7
4.0
250
4.7
4.0
250
4.7
4.0
15
170
450
15
0.5
1
2
90
9.0
53
1.30
10
+1.25
110
10
700
1000
V p-p
V p-p
ppm/°C
μA
μA
pF
M
mV
% FS
% FS
V
ppm/°C
MSPS
MSPS
ns
μs
μs
ns
μs
μs
ns
μs
μs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
Rev. C | Page 4 of 36